Multi-format multiplier unit
AssigneeAnalog Devices, Inc.
InventorsAndreas D. Olofsson, Baruch Yanovitch
Life of this patent
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Abstract
Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.
Claims19
A multiplication engine for a digital processor, the multiplication engine comprising:
- a first partial-product generation circuit to generate a first set of unequally weighted partial products from a set of input operands;
- a second partial-product generation circuit to generate a second set of equally weighted partial products from the set of input operands;
- a multiplexer to select the first set of unequally weighted partial products or the second set of equally weighted partial products in accordance with first and second multiplier modes, respectively;
- and
- a carry save adder array configured to add the selected set of partial products,
- wherein, in the first multiplier mode, the carry-save adder array folds over higher-order bits of the first set of unequally weighted partial products into lower-order slots in the carry-save adder array, thereby allowing the same carry-save adder array to be used in either the first or the second multiplier modes.
A method for multiplication in a digital processor, comprising:
- generating a first set of unequally weighted partial products from a set of input operands;
- generating a second set of equally weighted partial products from the set of input operands;
- selecting the first set of unequally weighted partial products when operating in a first multiplier mode or selecting the second set of equally weighted partial products when operating in a second multiplier mode;
- folding over, in the carry-save adder array, higher-order bits of the first set of unequally weighted partial products into lower-order slots in the carry-save adder array when operating in the first multiplier mode, thereby allowing the carry-save adder array to be used in the first and second multiplier modes;
- and
- adding the selected set of partial products in a carry save adder array comprising digital logic circuitry.
Dependencies are inferred from the claim text.