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US 8,275,728 B2Granted
Neuromorphic computer
AssigneeThe United States of America as represented by the Secretary of the Air Force
InventorRobinson E. Pino
Life of this patent
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Abstract
A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.
Claims1
A neuromorphic computing device, comprising:
- at least one input;
- at least one output;
- and
- a plurality of synapse circuits electrically interconnecting said at least one input to said at least one output, wherein;
- said synapse circuit further comprises
- an input;
- an output;
- and
- a variable resistance element having an input and an output, wherein said variable resistance element controls the connection strength between said synapse circuits;
- and wherein
- said variable resistance element further comprises a transistor biased in its linear operating region, wherein said output of said synapse circuit outputs a signal SO(SI, Vm) according to the relationship
- O
-
- (
- S
-
-
- I
- ,
- V
- m
- )
- =
- -
- 4
- *
- [
- μ
- n
-
- C
- ox
-
- W
- L
-
- (
- (
- V
- m
- -
- V
- th
- )
-
- S
-
-
- I
- -
- SI
- 2
- )
- 2
-
- R
- ]
- +
- 2
-
- V
- wherein
- SI is the input to said synapse in voltage units;
- Vm is a biasing weight voltage of said transistor;
- W is the width of said gate of said transistor;
- L is the length of said gate of said transistor;
- Cox is the gate oxide capacitance of said transistor;
- R is the value of a biasing resistor used to control the potential output of said synapse;
- Vth is the threshold voltage of said transistor;
- and
- μn is electron mobility of said transistor.
68 more elements
Dependencies are inferred from the claim text.