Software table walk during test verification of a simulated densely threaded network on a chip
AssigneeInternational Business Machines Corporation
InventorsAnatoli S. Andreev, Olaf K. Hendrickson, John M. Ludden, Richard D. Peterson, Elena Tsanko
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Abstract
A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.
Claims20
A computer-implemented method of performing a software table walk during test verification in a computer simulation, the computer-implemented method comprising utilizing a specific hardware system that performs the steps of:
- loading a Translation Lookaside Buffer (TLB) interrupt handler into a test generator, wherein the test generator randomly generates instructions for a test program to be virtually executed within a computer simulation;
- populating the computer simulation with at least one Translation Lookaside Buffer (TLB), wherein the TLB contains a sub-set of entries from a page table, wherein entries from the page table map a virtual address to a real address in the computer simulation, and wherein the virtual address is for data used by an instruction from the test program;
- utilizing the test generator to generate the test program;
- stripping said at least one TLB from the computer simulation;
- executing a first instruction from the test program in the computer simulation;
- in response to the test program detecting a TLB miss of a needed virtual page that is required to execute the first instruction, utilizing the TLB interrupt handler to walk the page table until the needed virtual page is located;
- writing the needed virtual page to the TLB;
- and
- completing execution of the first instruction by using the needed virtual page from the TLB.
A computer system comprising:
- a system bus;
- a processor coupled to the system bus;
- a memory coupled to the system bus, wherein the memory stores computer executable instructions that, when executed, perform a software table walk during test verification in a computer simulation by performing the steps of:
- loading a Translation Lookaside Buffer (TLB) interrupt handler into a test generator, wherein the test generator randomly generates instructions for a test program to be virtually executed within a computer simulation;
- populating the computer simulation with at least one Translation Lookaside Buffer (TLB), wherein the TLB contains a sub-set of entries from a page table, wherein entries from the page table map a virtual address to a real address in the computer simulation, and wherein the virtual address is for data used by an instruction from the test program;
- utilizing the test generator to generate the test program;
- stripping said at least one TLB from the computer simulation;
- executing a first instruction from the test program in the computer simulation;
- in response to the test program detecting a TLB miss of a needed virtual page that is required to execute the first instruction, utilizing the TLB interrupt handler to walk the page table until the needed, virtual page is located;
- writing the needed virtual page to the TLB;
- and
- completing execution of the first instruction by using the needed virtual page from the TLB.
A non-transitory computer-readable storage medium on which is encoded a computer program, the computer program comprising computer executable instructions configured for performing a software table walk during test verification in a computer simulation by performing the steps of:
- loading a Translation Lookaside Buffer (TLB) interrupt handler into a test generator, wherein the test generator randomly generates instructions for a test program to be virtually executed within a computer simulation;
- populating the computer simulation with at least one Translation Lookaside Buffer (TLB), wherein the TLB contains a sub-set of entries from a page table, wherein entries from the page table map a virtual address to a real address in the computer simulation, and wherein the virtual address is for data used by an instruction from the test program;
- utilizing the test generator to generate the test program;
- stripping said at least one TLB from the computer simulation;
- executing a first instruction from the test program in the computer simulation;
- in response to the test program detecting a TLB miss of a needed virtual page that is required to execute the first instruction, utilizing the TLB interrupt handler to walk the page table until the needed virtual page is located;
- writing the needed virtual page to the TLB;
- and
- completing execution of the first instruction by using the needed virtual page from the TLB.
Dependencies are inferred from the claim text.