MAC controlled sleep mode/wake-up mode with staged wake-up for power management devices
AssigneeBroadcom Corporation
InventorsMark D. Matson, Bruce E. Edwards
Life of this patent
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Abstract
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
Claims20
An apparatus comprising:
- a processor for a wireless communication device that includes an instruction pipeline;
- and
- a power control logic to detect a sleep instruction and to place the processor in a low-power state after completing any preceding instruction or instructions still in the instruction pipeline, and in which the power control logic is operable in response to a wake-up signal to reactivate the instruction pipeline to process a subsequent instruction following the sleep instruction to perform processing tasks associated with the wake-up signal.
A method comprising:
- detecting a sleep instruction in a power control logic associated with a processor for a wireless communication device, in which the processor includes an instruction pipeline for executing instructions;
- stopping fetch of new instructions after encountering the sleep instruction;
- completing any preceding instruction or instructions still in the instruction pipeline in response to the sleep instruction;
- placing the processor in a low-power state after completing any preceding instruction or instructions still in the instruction pipeline;
- reactivating the instruction pipeline to process a subsequent instruction following the sleep instruction in response to a wake-up signal;
- and
- performing processing tasks associated with the subsequent instruction following the sleep instruction in response to the wake-up signal.
A processor for a wireless communication device comprising:
- a processing unit for the wireless communication device that includes an instruction pipeline;
- and
- a power control logic to detect a sleep instruction and to place the processing unit in a low-power state after completing any preceding instruction or instructions still in the instruction pipeline, and in which the power control logic is operable in response to a wake-up signal to reactivate the instruction pipeline to process a subsequent instruction following the sleep instruction to perform processing tasks associated with the wake-up signal.
Dependencies are inferred from the claim text.