Back to results
US 8,274,852 B2Granted
Semiconductor memory apparatus and method of testing the same
AssigneeHynix Semiconductor Inc.
InventorYoung Soo Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a sense amplifier coupled to a plurality of bit lines, a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal, a mode selecting unit configured to selectively couple the first node to a pad or a ground terminal in response to a mode selection signal and a testing unit configured to supply current to the pad during a test mode.
Claims14
A method of testing a semiconductor memory apparatus comprising:
- combining address codes to generate a mode selection signal;
- and
- causing a plurality of bit lines to be coupled to a pad by enabling a switching signal at a read timing when the mode selection signal instructs a test mode.
A semiconductor memory apparatus comprising:
- a memory block including a plurality of memory cells coupled to a plurality of bit lines;
- a sense amplifier coupled to the plurality of bit lines;
- a modeling cell array including a plurality of memory cells coupled to the sense amplifier, each memory cell of the modeling cell array being coupled to a bit line of the plurality of bit lines and selectively coupled to a first node;
- and
- a switching unit coupled to each of the memory cells of the modeling cell array and responsive to a switching signal to cause the plurality of bits fines to be coupled to the first node, wherein the first node receives a current for testing the sense amplifier when a test mode is enabled.
2 more elements
A semiconductor memory apparatus comprising:
- a sense amplifier coupled to a plurality of bit lines;
- a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal;
- a mode selecting unit configured to selectively couple the first node to a pad or a ground terminal in response to a mode selection signal, wherein the pad receives a current and the first node is coupled to the pad during a test mode and the mode selection signal is implemented by a combination of an address having a plurality of bits;
- a memory block including a plurality of memory cells that are each coupled to a word line and a bit line of the plurality of bit lines;
- and
- a modeling cell array including a plurality of memory cells that are provided between the memory block and the sense amplifier, each memory cell of the modeling cell array being coupled to a bit line of the plurality of bit lines.
3 more elements
Dependencies are inferred from the claim text.