Reference voltage generation circuit and semiconductor memory

A semiconductor memory comprising:

• a memory cell;
• and
• a reference voltage generation circuit configured to generate a voltage for the memory cell, wherein
• the reference voltage generation circuit comprises:
• a first node settable at a first voltage to be any one of a plurality of voltage levels;
• a second node configured to be set at a second voltage;
• first and second switches connected in series between the first and second nodes;
• a plurality of capacitors, each capacitor comprising a first and second end, the first end of each capacitor connected to a connection node between the first and second switches, the second end of each capacitor settable at a voltage level independent of a voltage level set at the second end of each other capacitor;
• a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch and to turn on the first switch;
• and
• a voltage controller configured to individually set the voltage at the second end of each of the plurality of capacitors after the first switch is turned on.

A reference voltage generation circuit comprising:

• a first node settable at a first voltage to be any one of a plurality of voltage levels;
• a first switch connected to the first node;
• a plurality of capacitors, each capacitor comprising a first and second end, the first end of each capacitor connected to a connection node connected to the first switch, the second end of each capacitor settable at a voltage level independent of a voltage level set at the second end of each other capacitor;
• a switch controller configured to turn off the first switch in an initial state, and then to turn on the first switch;
• and
• a voltage controller configured to individually set the voltage at the second end of each of the plurality of capacitors after the first switch is turned on.