Semiconductor device having nonvolatile memory element and data processing system including the same
AssigneeElpida Memory, Inc.
InventorsYoshio Mizukane, Hiroki Fujisawa
Life of this patent
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Abstract
A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.
Claims19
A semiconductor device comprising:
- a timing control circuit producing first and second reset signals, the first reset signal taking an active level during the second reset signal taking an inactive level, and the second reset signal taking an active level during the first reset signal taking an inactive level;
- an information storing element;
- a read-out circuit coupled to the timing control circuit and the information storing element and activated in response to the active level of the first reset signal to read out information stored in the information storing element;
- and
- an SR latch circuit including a set terminal supplied with an output from the read-out circuit and a reset terminal supplied with the second reset signal, the SR latch circuit being cleared in response to the active level of the second reset signal.
A semiconductor device comprising:
- a timing control circuit producing first and second reset signals, the first reset signal taking an active level during a first period of time, the second reset signal taking an active level during a second period of time;
- an information storage element;
- a read-out circuit coupled to the timing control circuit and the information storage element and activated in response to the active level of the first reset signal to read out information stored in the information storage element and produce an output signal related to the information;
- and
- a latch circuit including a first input terminal and a second input terminal provided independently of the first input terminal, the first input terminal being coupled to the read-out circuit to receive the output signal from the read-out circuit, the second input terminal being coupled to the timing control circuit to receive the second reset signal, the latch circuit being cleared in response to the active level of the second reset signal.
A semiconductor device comprising:
- a timing control circuit producing first and second reset signals, the first reset signal taking an active level during a first period of time, the second reset signal taking an active level during a second period of time;
- a storage circuit comprising,
- an information storage element,
- a read-out circuit coupled to the timing control circuit and the information storage element and activated in response to the active level of the first reset signal to read out information stored in the information storage element,
- a first latch circuit temporarily storing the information and producing an output signal related to the information, and
- a second latch circuit including a first input terminal and a second input terminal provided independently of the first input terminal, the first input terminal being coupled to the first latch circuit to receive the output signal, the second input terminal being coupled to the timing control circuit to receive the second reset signal, the second latch circuit being cleared in response to the active level of the second reset signal;
- and
- a main circuit performing a circuit operation in response to an output of the latch circuit.
Dependencies are inferred from the claim text.