Variable impedance memory device having simultaneous program and erase, and corresponding methods and circuits

An integrated circuit, comprising:

• a plurality of programmable metallization cells (PMCs) each comprising a solid ion conducting material formed between a first electrode and a second electrode, the second electrodes being coupled to bit lines;
• a node decoder circuit that couples first electrodes between at least a first voltage and second voltage in response to at least first address data;
• a plurality of read circuits, each coupled to second electrodes of the PMCs by at least an access device, each read circuit determining a stored data value of an accessed PMC;
• and
• a plurality of write circuits, each coupled to second electrodes of the PMCs by at least an access device, each write circuit applying at least a program voltage or an erase voltage to an accessed PMC in response to an input write data value, each write circuit being disabled in response to a comparison between a determined stored data value and a corresponding input write data value.

An integrated circuit, comprising:

• a plurality of programmable metallization cells (PMCs) each comprising a solid ion conducting material formed between a first electrode and a second electrode, the second electrodes being coupled to bit lines;
• a bit line decoder circuit that couples bit lines to at least a bit line program voltage or a bit line erase voltage in response to address data;
• and
• a node decoder circuit that couples first electrodes between at least a first voltage and second voltage in response to at least first address data;
• wherein
• each PMC device is erased to at least a first impedance state in response to its first electrode being coupled to the first voltage while its second electrode is coupled to the bit line erase voltage, and programmed to at least a second impedance state in response to its first electrode being coupled to the second voltage while its second electrode is coupled to the bit line program voltage.