Method of erasing a flash EEPROM memory

A method for erasing a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics, the method comprising the steps of:

• applying a first voltage bias of negative polarity to both the well electrode and the second semiconductor region and applying a first zero voltage bias to the control gate electrode for a duration of traps depopulation;
• after the duration of traps depopulation, applying a second voltage bias of positive polarity to the control gate electrode and a second zero voltage bias to both the well electrode and the second semiconductor region for a duration of traps assisted tunneling;
• and
• after the duration of traps assisted tunneling, applying a third voltage bias of positive polarity to the control gate electrode and a fourth voltage bias of negative polarity to both the well electrode and the second semiconductor region for a duration of F/N tunneling.

A method for erasing a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics, the method comprising the steps of:

• applying a first voltage bias to both the well electrode and the second semiconductor region and a second voltage bias to the control gate electrode for a duration of F/N tunneling;
• applying a third voltage bias to both the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation;
• and
• after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to both the well electrode and the second semiconductor region for a duration of traps assisted tunneling.