NAND flash memory
AssigneeKabushiki Kaisha Toshiba
InventorDai Nakamura
Life of this patent
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Abstract
A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation.
Claims20
A NAND flash memory comprising:
- a semiconductor substrate;
- a well region in the semiconductor substrate;
- memory cells connected in series in the well region;
- a discharge circuit connected to the well region;
- a word line connected to the memory cells;
- and
- a control circuit which controls potentials of the well region and the word line,
- wherein the control circuit sets the well region to a first potential, and sets the word line to a second potential lower than the first potential, to execute an erase operation,
- wherein the discharge circuit discharges the well region after the erase operation,
- wherein the control circuit sets the word line to a third potential higher than the second potential after setting the well region to the first potential and before starting a discharge of the well region by using the discharge circuit.
A NAND flash memory comprising:
- a semiconductor substrate;
- a well region in the semiconductor substrate;
- first and second memory blocks in the well region;
- a discharge circuit connected to the well region;
- first word lines connected to memory cells in the first memory block;
- second word lines connected to memory cells in the second memory block;
- control gate lines which are shared by the first and second memory blocks;
- first transfer transistors between the first word lines and the control gate lines;
- second transfer transistors between the second word lines and the control gate lines;
- and
- a control circuit which is configured to:
- execute an erase operation of the memory cells in the first memory block by setting the well region to a first potential, setting the first word lines to a second potential lower than the first potential, and setting the second word lines to a floating state;
- discharge the well region by using the discharge circuit after the erase operation;
- and
- keep the floating state of the second word lines by setting the control gate lines and the first word lines to a third potential higher than the second potential after setting the well region to the first potential and before starting a discharge of the well region by using the discharge circuit.
Dependencies are inferred from the claim text.