# US 8,274,832 B2 · Dynamic polarization for reducing stress induced leakage current > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,274,832 B2 - Document ID: US8274832B2 - Status: Granted - Kind: B2 - Application number: 13/089,259 - Filed: 2011-04-18 - Published: 2011-10-13 - Granted: 2012-09-25 - Earliest claimed: 2008-12-30 - Assignees: Micron Technology, Inc. - Inventors: Luca Chiavarone; Mattia Robustelli; Angelo Visconti - Web page: https://patentgrep.com/patent/US8274832B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current. ## Claims ### Claim 1 A method comprising: operating a non-volatile memory device in a standby mode; and applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device while storing a “0” state in said memory cell and while said non-volatile memory device is operating in said standby mode, wherein said “0” state corresponds to said floating gate being negatively charged. ### Claim 2 (depends on 1) The method of claim 1, wherein said non-volatile memory device comprises a flash memory device. ### Claim 3 (depends on 1) The method of claim 1, wherein said voltage wave-form is applied via a body of said memory cell. ### Claim 4 (depends on 1) The method of claim 1, wherein said applying said voltage wave-form comprises applying a square wave voltage to said memory cell, wherein said square wave voltage includes a positive voltage portion and a negative voltage portion. ### Claim 5 (depends on 1) The method of claim 1, further comprising sequentially applying said voltage wave-form to individual word-lines of said non-volatile memory device. ### Claim 6 (depends on 1) The method of claim 1, further comprising sequentially applying said voltage wave-form to individual blocks of said non-volatile memory device. ### Claim 7 (depends on 1) The method of claim 1, further comprising applying said voltage wave-form to said non-volatile memory device in response to stress induced leakage current (SILC) in said non-volatile memory device. ### Claim 8 (depends on 1) The method of claim 1, wherein said electric field inhibits electrons on said floating gate from tunneling to said substrate. ### Claim 9 A method comprising: operating a non-volatile memory device in a standby mode; applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device while said non-volatile memory device is operating in said standby mode; and applying said voltage wave-form to a block of memory cells of said non-volatile memory device during said standby mode operation, wherein said voltage wave-form comprises a first amplitude portion having a first time span and a second amplitude portion having a second time span, and wherein said first and second time spans are based, at least in part, on a thickness of an oxide layer between said floating gate and said substrate. ### Claim 10 An apparatus comprising: a non-volatile memory cell array including a memory cell having a floating gate; and a controller to apply a voltage wave-form to said memory cell to generate an electric field between said floating gate and a substrate of said memory cell during a set state in said memory cell during a standby mode operation of said memory cell, wherein said set state corresponds to said floating gate being negatively charged. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein said memory cell array comprises a flash memory cell array. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein said voltage wave-form comprises a square wave voltage, wherein said square wave voltage includes a positive voltage portion and a negative voltage portion. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein said voltage wave-form comprises a pulsed voltage to generate a pulsed electric field between said floating gate and said substrate of said memory cell. ### Claim 14 (depends on 10) The apparatus of claim 10, wherein said voltage wave-form is applied via a body of said memory cell. ### Claim 15 (depends on 10) The apparatus of claim 10, further comprising sequentially applying said voltage wave-form to individual word-lines of said non-volatile memory device. ### Claim 16 (depends on 10) The apparatus of claim 10, further comprising applying said voltage wave-form to said non-volatile memory device in response to stress induced leakage current (SILC) in said non-volatile memory device. ### Claim 17 (depends on 10) The apparatus of claim 10, further comprising a processor to host one or more applications and to initiate programming said non-volatile memory cell array. ### Claim 18 An apparatus comprising: means for operating a non-volatile memory device in a standby mode; and means for applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device to inhibit electrons on said floating gate from tunneling to said substrate while storing a “0” state in said memory cell and during said standby mode operation, wherein said “0” state corresponds to said floating gate being negatively charged. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein said non-volatile memory device comprises a flash memory device. ### Claim 20 (depends on 19) The apparatus of claim 19, further comprising: means for storing a “0” state in said memory cell, wherein said “0” state corresponds to a negatively charged floating gate responsive at least in part to said voltage wave-form. ### Claim 21 (depends on 18) The method of claim 18, further comprising: means for applying said voltage wave-form to a block of memory cells of said non-volatile memory device during said standby mode operation, wherein said voltage wave-form comprises a first amplitude portion having a first time span and a second amplitude portion having a second time span, and wherein said first and second time spans of said voltage wave-form are based, at least in part, on a thickness of an oxide layer between said floating gate and said substrate.