# US 8,274,830 B2 · Constant current read mode or constant current data retention mode nonvolatile memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,274,830 B2
- Document ID: US8274830B2
- Status: Granted
- Kind: B2
- Application number: 12/462,910
- Filed: 2009-08-11
- Published: 2010-02-25
- Granted: 2012-09-25
- Earliest claimed: 2008-08-12
- Assignees: Seiko Instruments Inc.
- Inventors: Kazuhiro Tsumura
- Web page: https://patentgrep.com/patent/US8274830B2

## CPC

- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 16/30: Power supply circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof comprises a constant current circuit and a non-volatile memory cell connected in series. A connection point between the constant current source and the non-volatile memory cell is selected to be an output to thereby enable writing, in a reading mode or a retention mode, in the non-volatile memory cell which is in a write state. The non-volatile semiconductor memory circuit includes a power supply for data reading and retaining and a power supply for data rewriting which are provided independently, and a transistor connected between the output and the power supply for data rewriting, in which the transistor is brought into conduction state when data is rewritten.

## Claims

### Claim 1

A non-volatile semiconductor memory circuit, comprising:
a non-volatile memory cell having an erase state in which a threshold voltage is low and a write state in which the threshold voltage is high to thereby store data;
a constant current circuit connected in series with the non-volatile memory cell; and
a connection point between the non-volatile memory cell and the constant current circuit being set to be an output;
wherein, in a reading mode or a retention mode, in which a voltage is applied to the non-volatile memory cell, the following relationship is satisfied:
IWRITE<ICONST<IERASE,
where a saturation current flowing through the non-volatile memory cell in the erase state is represented by IERASE, a saturation current flowing through the non-volatile memory cell in the write state is represented by IWRITE, and a constant current provided from the constant current circuit is represented by ICONST.

### Claim 2 (depends on 1)

The non-volatile semiconductor memory circuit according to claim 1, wherein in one of the reading mode and the retention mode:
in a case where the non-volatile memory cell is in the erase state, a voltage applied between a source and a drain of the non-volatile memory cell is made to be close to 0 V, to thereby prevent writing in the non-volatile memory cell which is in the erase state; and
in a case where the non-volatile memory cell is in the write state, the voltage applied between the source and the drain of the non-volatile memory cell is made to be close to a power supply voltage higher than another power supply voltage, to thereby allow writing in the non-volatile memory cell which is in the write state by hot electrons.

### Claim 3 (depends on 1)

The non-volatile semiconductor memory circuit according to claim 1, further comprising:
a power supply line used in the reading mode and the retention mode;
another power supply line which is provided separately from the power supply line and is used in data rewriting of the non-volatile memory cell; and
a transistor provided between the output and the another power supply line used in the data rewriting of the non-volatile memory cell;
wherein the transistor is brought into conduction state at a time of the data rewriting of the non-volatile memory cell.

### Claim 4 (depends on 1)

The non-volatile semiconductor memory circuit according to claim 1; wherein the constant current flows constantly through a circuit formed of the constant current circuit and the non-volatile memory cell which are connected in series while a power supply voltage is applied to the circuit.

### Claim 5 (depends on 1)

The non-volatile semiconductor memory circuit according to claim 1; wherein the constant current circuit comprises a MOS transistor which is in a saturated operating state.