Structures and methods for reading out non-volatile memory using referencing cells

A method of reading a nonvolatile memory (NVM) cell comprising the steps of:

• applying a pre-charge voltage to a first capacitor and a second capacitor during a charge period, wherein the NVM cell is connected in parallel with the first capacitor and a reference NVM cell is connected in parallel with the second capacitor;
• applying a gate voltage to a control gate of the NVM cell and a control gate of the reference NVM cell to discharge the first capacitor and the second capacitor through the NVM cell and the reference NVM cell during an elapsing period and a sensing period;
• and
• sensing a difference between a first voltage level across the first capacitor and a second voltage level across the second capacitor during the sensing period;
• wherein capacitances of the first capacitor and the second capacitor are substantially equivalent.

A NOR nonvolatile memory (NVM) device, comprising:

• a plurality of NVM cells arranged in rows and columns in NOR configuration;
• a reference cell connected to a reference bit line;
• a plurality of first capacitors;
• a second capacitor;
• a plurality of bit lines each connected to a specified number of the NVM cells;
• and
• a plurality of sense amplifiers each having a first input terminal connected to both one of the first capacitors and one of at least one selected bit line and a second input terminal connected to both the second capacitor and the reference bit line;
• wherein each of the first capacitors is configured to charge a corresponding selected bit line to a read voltage and the second capacitor is configured to charge the reference bit line to the read voltage;
• wherein when a control gate of the reference cell and a selected word line are biased with a gate voltage, the reference bit line and each selected bit line are discharged through the reference cell and each corresponding selected NVM cell;
• and
• wherein capacitances of the first capacitors and the second capacitor are substantially equivalent.

A method of reading a NOR nonvolatile memory device having a plurality of NVM cells arranged in rows and columns in NOR configuration, a reference cell and a plurality of sense amplifiers, each of the sense amplifiers having a first input terminal connected to both one of a plurality of first capacitors and a corresponding selected bit line and a second input terminal connected to both a second capacitor and a reference bit line, the method comprising the steps of:

• applying a read voltage to both the first capacitor of each selected bit line and the second capacitor in order to pre-charge each selected bit line and the reference bit line to a preset voltage during a charge period;
• applying a gate voltage to both a control gate of the reference cell and a selected word line to discharge the reference bit line and each corresponding selected bit line through the reference cell and each corresponding selected NVM cell during an elapsing period and a sensing period;
• and
• sensing a voltage difference between the reference bit line and the corresponding selected bit line by means of each of the sense amplifiers during the sensing period;
• wherein capacitances of the first capacitors and the second capacitor are substantially equivalent.

A NAND nonvolatile memory (NVM) device, comprising:

• a NAND memory array having a plurality of NAND strings arranged therein, each NAND string having a plurality of NVM cells connected in series;
• a reference NAND string having a plurality of reference cells connected in series, the reference NAND string being connected to a reference bit line;
• a plurality of first capacitors;
• a second capacitor;
• a plurality of bit lines each connected to one of the NAND strings;
• and
• a plurality of sense amplifiers each having a first input terminal connected to both one of the first capacitors and a corresponding bit line and a second input terminal connected to both the second capacitor and the reference bit line;
• wherein each of the first capacitors is configured to charge the corresponding bit line to a read voltage and the second capacitor is configured to charge the reference bit line to the read voltage;
• wherein when a selected word line is biased with a gate voltage, the reference bit line and each bit line are discharged through the reference cell and each corresponding selected NVM cell;
• and
• wherein capacitances of the first capacitors and the second capacitor are substantially equivalent.

A method of reading a NAND nonvolatile memory device having a NAND memory array, a reference NAND string and a plurality of sense amplifiers, the NAND memory array having a plurality of NAND strings arranged therein, each of the sense amplifiers having a first input terminal connected to both one of a plurality of first capacitors and a corresponding bit line and a second input terminal connected to both a second capacitor and a reference bit line, the method comprising the steps of:

• applying a read pass voltage to a plurality of unselected word lines in at least one selected NAND string and the reference NAND string;
• applying a read voltage to each first capacitor of each bit line and the second capacitor to pre-charge each bit line and the reference bit line to a preset voltage during a charge period;
• applying a gate voltage to a selected word line to discharge the reference bit line and each bit line through a selected reference cell and each corresponding selected NVM cell during an elapsing period and a sensing period;
• and
• sensing a voltage difference between the selected reference bit line and the corresponding bit line by means of each of the sense amplifiers during the sensing period;
• wherein capacitances of the first capacitors and the second capacitor are substantially equivalent.