Memory device and operating method thereof

A memory device on a substrate, comprising

• a plurality of semiconductor layers stacked on one another on the substrate, wherein each of the semiconductor layers has a plurality of NAND strings, and each of the NAND strings includes a plurality of memory cells and at least a string selection transistor, and each of the NAND strings has a first end and a second end;
• a plurality of common word lines, wherein each of the common word lines is coupled to the memory cells arranged in a same row of the plurality of semiconductor layers stacked on one another;
• a plurality of common bit lines, wherein each of the common bit lines is coupled to the first ends of the NAND strings arranged in the same column of the semiconductor layers through a bit line contact, and a bit line contact area between the bit line contact and each of the first ends of the NAND strings arranged in the same column of the semiconductor layers is a first heavily doped area with a single conductive type;
• and
• a common source line, wherein the common source line is coupled to the second ends of the NAND strings of the semiconductor layers through a source line contact and a source line contact area between the source line contact and each of the second ends of the NAND strings of the semiconductor layers is a second heavily doped area with the single conductive type.

A method for operating a memory device, wherein the memory device comprises a plurality of semiconductor stacked layers of a plurality of NAND strings, and each of the NAND strings has a first end and a second end, and each of the NAND strings includes a plurality of memory cells serially connected to one another, and the memory device further comprises a plurality of common word lines, and each of the common word lines is coupled to the memory cells arranged in a same row of the semiconductor layers, the method comprising:

• performing an erasing operation on the memory cells of a selected NAND string from the NAND strings, wherein the erasing operation comprises:
• applying a first voltage on the common word lines respectively coupled to the memory cells of the selected NAND string and applying a second voltage on a common source line coupled to the second end of the selected NAND string;
• sequentially erasing the memory cells of the selected NAND string from the first end to the second end of the selected NAND string if the common word lines are sequentially grounded from the first end to the second end of the selected NAND string;
• sequentially erasing the memory cells of the selected NAND string from the second end to the first end of the selected NAND string if the common word lines are sequentially grounded from the second end to the first end of the selected NAND string;
• selectively erasing the memory cells selected from the memory cells of the selected NAND string if the common word lines respectively coupled to the selected memory cells are grounded at the same time;
• erasing a continuous portion of memory cells of the selected NAND string if the common word lines respectively coupled to the continuous portion of the memory cells are grounded at the same time;
• and
• erasing all of the memory cells of the selected NAND string at the same time if the common word lines respectively coupled to the memory cells of the selected NAND string are all grounded at the same time.