US 8,274,824 B1 · High-performance CMOS-compatible non-volatile memory cell and related method

Abstract

A memory cell includes a control gate and a transistor having a gate, a source junction, and a drain junction. The gate is coupled to the control gate, and the source junction and the drain junction are asymmetrical. For example, a channel doping associated with the source junction may be different than a channel doping associated with the drain junction. The memory cell also includes a write line coupled to the control gate, a source line coupled to the source junction of the transistor, and a bit line coupled to the drain junction of the transistor. The control gate could represent a second transistor, where the gates of the transistors are coupled together to form a floating gate. The memory cell could be programmed to store a single-bit value or a multiple-bit value, such as by storing the appropriate charge on the floating gate.

Claims17

Dependent claims

A memory cell comprising:

a control gate;
a transistor having a gate, a source junction, and a drain junction, wherein the gate is coupled to the control gate, and wherein the source junction and the drain junction are asymmetrical;
a write line coupled to the control gate;
a source line connected to the source junction of the transistor;
and
a bit line coupled to the drain junction of the transistor, wherein:
the transistor comprises a first transistor;
and the control gate comprises a second transistor, the second transistor having a gate coupled to the gate of the first transistor to form a floating gate, and the second transistor has a source, a drain, and a substrate directly coupled to the write line.

5 more elements

Dependencies are inferred from the claim text.

High-performance CMOS-compatible non-volatile memory cell and related method

Life of this patent

High-performance CMOS-compatible non-volatile memory cell and related method

Life of this patent

Abstract

Claims17