Non volatile memory device ion barrier

A non-volatile memory device, comprising:

• a substrate including active circuitry fabricated front-end-of-the-line (FEOL) on the substrate;
• a plurality of first conductive array lines;
• a plurality of second conductive array lines;
• and
• a plurality of two-terminal memory cells, each memory cell including a first terminal in electrical communication with only one of the plurality of first conductive array lines and a second terminal in electrical communication with only one of the plurality of second conductive array lines, the plurality of two-terminal memory cells and the plurality of first and second conductive array lines are fabricated back-end-of-the-line (BEOL) in one or more memory layers in contact with and positioned over the substrate with the plurality of first and second conductive array lines in electrical communication with at least a portion of the active circuitry, each two-terminal memory cell including a re-writeable non-volatile memory element (ME) having exactly two terminals and including electrically in series with its two terminals
• an ion reservoir including mobile ions,
• a tunnel barrier layer in direct contact with the ion reservoir, the tunnel barrier layer is permeable to the mobile ions, and
• an ion barrier layer in direct contact with the tunnel barrier layer, the ion barrier layer is not permeable to the mobile ions and is operative to prevent mobile ion transport through an interface where the ion barrier layer and the tunnel barrier layer directly contact each other,
• the ME retains stored data in the absence of electrical power and the ME includes a non-linear resistance that is a not a linear function of a voltage applied across the two terminals.

An electrical system, comprising:

• a bus;
• a processing unit in electrical communication with the bus;
• an input/output (I/O) unit in electrical communication with the bus;
• and
• a memory unit electrically coupled with the processing unit, the memory unit including
• a substrate including active circuitry fabricated front-end-of-the-line (FEOL) on the substrate,
• a plurality of first conductive array lines,
• a plurality of second conductive array lines, and
• a plurality of two-terminal memory cells, each two-terminal memory cell including a first terminal in electrical communication with only one of the plurality of first conductive array lines and a second terminal in electrical communication with only one of the plurality of second conductive array lines, the plurality of two-terminal memory cells and the plurality of first and second conductive array lines are fabricated back-end-of-the-line (BEOL) in one or more memory layers in contact with and positioned over the substrate with the plurality of first and second conductive array lines in electrical communication with at least a portion of the active circuitry, each two-terminal memory cell including a re-writeable non-volatile memory element (ME) having exactly two terminals and including electrically in series with its two terminals
• an ion reservoir including mobile ions,
• a tunnel barrier layer in direct contact with the ion reservoir, the tunnel barrier layer is permeable to the mobile ions, and
• an ion barrier layer in direct contact with the tunnel barrier layer, the ion barrier layer is not permeable to the mobile ions and is operative to prevent mobile ion transport through an interface where the ion barrier layer and the tunnel barrier layer directly contact each other, the ME retains stored data in the absence of electrical power and the ME includes a non-linear resistance that is a not a linear function of a voltage applied across the two terminals.