Serializer with odd gearing ratio
AssigneeLattice Semiconductor Corporation
InventorsFulong Zhang, Ling Wang, John Schadt
Life of this patent
Estimating the term…
Abstract
In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N−1 operating mode (that serializes (N−1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.
Claims20
An integrated circuit having a serializer (e.g., 100) adapted to serialize N-bit parallel data, where N is an odd integer, the serializer comprising:
- a transfer stage (e.g., 102) connected to transfer the N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain;
- an update stage (e.g., 104, 106) connected to receive parallel data from the transfer stage;
- and
- a serializing stage (e.g., 108, 110) connected to convert parallel data received from the update stage into serial data having N-bit data words, wherein the update stage is selectively configurable to cause the serializer to operate in either (i) an N−1 operating mode in which (N−1) bits of parallel data are serialized or (ii) an N+1 operating mode in which (N+1) bits of parallel data are serialized.
An integrated circuit having a serializer adapted to serialize an N-bit parallel data stream where N is an odd integer, the serializer comprising:
- a stage of transfer registers (e.g., 102) connected to process parallel data bits from the N-bit parallel data stream based on a first clock signal (e.g., SCLK);
- a stage of update registers (e.g., 106) connected to process parallel data bits from the stage of transfer registers based on a second clock signal (e.g., ECLK) faster than the first clock signal;
- and
- a stage of shift registers (e.g., 110) connected to convert parallel data bits from the stage of update registers into an outgoing serial data stream based on the second clock signal.
Dependencies are inferred from the claim text.