Automatic frequency control architecture with digital temperature compensation

A phase lock loop (PLL) system, comprising:

• a voltage controlled oscillator, including:
• a tank circuit having a capacitor and an inductor and for providing an oscillating frequency in response to a control voltage;
• a control block responsive to a frequency control signal and for adjusting oscillation frequency, wherein the voltage controlled oscillator is associated with a frequency verse control voltage curve having a first region for determining if a PLL lock condition is satisfied and defined by Vreflo and Vrefhi, where Vreflo is a lower voltage limit of the first region and Vrefhi is an upper voltage limit of the first region;
• and
• a post-lock temperature compensation block configured with a switchable multi-leg capacitor bank that is responsive to a digital temperature compensation control signal and for adjusting post-lock oscillation frequency;
• wherein the frequency verse control voltage curve has a second region defined by Vbot and Vtop, where Vbot is less than Vreflo and Vtop is greater than Vrefhi, such that the first region is within the second region;
• wherein in response to lock being acquired and the control voltage being greater than Vtop, capacitor legs of the multi-leg capacitor bank are sequentially disengaged until the control voltage is at an acceptable level;
• and
• wherein in response to lock being acquired and the control voltage being less than Vbot, capacitor legs of the multi-leg capacitor bank are sequentially engaged until the control voltage is at an acceptable level;
• a phase-frequency detector;
• a lock detector;
• a charge pump/loop filter;
• an automatic amplitude control circuit;
• and
• an automatic frequency control circuit for generating the frequency control signal, and configured with:
• a reset circuit for resetting the control voltage to a mid-range value between Vreflo and Vrefhi in response to the PLL lock condition not being satisfied and the control voltage being either greater than Vrefhi for a specified waiting time period or less than Vreflo for a specified waiting time period;
• and
• an AFC freeze control circuit for causing the automatic frequency control circuit to enter a freeze mode in response to lock being acquired and the control voltage being between Vreflo and Vrefhi for a specified waiting time period.

A phase lock loop (PLL) system, comprising:

• a voltage controlled oscillator, including:
• a tank circuit having a capacitor and an inductor and for providing an oscillating frequency in response to a control voltage;
• a control block responsive to a frequency control signal and for adjusting oscillation frequency, wherein the voltage controlled oscillator is associated with a plurality of frequency verse control voltage curves each having a first region for determining if a PLL lock condition is satisfied and defined by Vreflo and Vrefhi, where Vreflo is a lower voltage limit of the first region and Vrefhi is an upper voltage limit of the first region, and wherein the frequency control signal is binary coded and the control block includes a plurality of control circuits, each responsive to a corresponding bit of the frequency control signal and including a capacitance that can be switched-in to supplement capacitance of the tank circuit when that corresponding bit is active;
• and
• a post-lock temperature compensation block configured with a switchable multi-leg capacitor bank that is responsive to a digital temperature compensation control signal and for adjusting post-lock oscillation frequency, wherein the temperature compensation control signal is thermometer coded and each leg of the multi-leg capacitor bank is selectable by a corresponding bit of the temperature compensation control signal to supplement capacitance of the tank circuit when that corresponding bit is active;
• wherein capacitance range provided by the control block is larger in terms of capacitance and does not overlap with capacitance range provided by the post-lock temperature compensation block;
• wherein each of the frequency verse control voltage curves has a second region defined by Vbot and Vtop, where Vbot is less than Vreflo and Vtop is greater than Vrefhi, such that the first region is within the second region;
• wherein in response to lock being acquired and the control voltage being greater than Vtop, capacitor legs of the multi-leg capacitor bank are sequentially disengaged until the control voltage is at an acceptable level;
• wherein in response to lock being acquired and the control voltage being less than Vbot, capacitor legs of the multi-leg capacitor bank are sequentially engaged until the control voltage is at an acceptable level;
• a phase-frequency detector;
• a lock detector;
• a charge pump/loop filter;
• an automatic amplitude control circuit;
• and
• an automatic frequency control circuit for generating the frequency control signal, the automatic frequency control circuit including:
• a reset circuit for resetting the control voltage to a mid-range value between Vreflo and Vrefhi in response to the PLL lock condition not being satisfied and the control voltage being either greater than Vrefhi for a specified waiting time period or less than Vreflo for a specified waiting time period;
• an AFC freeze control circuit for causing the automatic frequency control circuit to enter a freeze mode in response to lock being acquired and the control voltage being between Vreflo and Vrefhi for a specified waiting time period;
• and
• a PFD control circuit for enabling the phase-frequency detector;
• wherein the multi-leg capacitor bank is activated to provide post-lock compensation only after lock is acquired and the automatic frequency control circuit enters the freeze mode, such that the control voltage stays locked on a selected one of the frequency verse control voltage curves as capacitor legs of the multi-leg capacitor bank are sequentially engaged and disengaged.