# US 8,274,331 B2 · Differential receiver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,274,331 B2 - Document ID: US8274331B2 - Status: Granted - Kind: B2 - Application number: 13/016,640 - Filed: 2011-01-28 - Published: 2012-08-02 - Granted: 2012-09-25 - Earliest claimed: 2011-01-28 - Assignees: Nanya Technology Corporation - Inventors: Yu Meng Chuang - Web page: https://patentgrep.com/patent/US8274331B2 ## CPC - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 1/0261: {with control of the polarisation voltage or current, e.g. gliding Class A} - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 3/45695: {by using feedforward means (H03F3/45744 takes precedence)} - H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages - H03F 2203/45244: the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors - H03F 2203/45508: the CSC comprising a voltage generating circuit as bias circuit for the CSC - H03F 2203/45702: the LC comprising two resistors - H03F: AMPLIFIERS ## Abstract A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained. ## Claims ### Claim 1 A differential receiver, comprising: a first amplifying circuit comprising: a first differential pair of PMOS transistors configured to receive first and second input voltages; a first current source connected between a supply voltage source and the first differential pair of PMOS transistors; and a first load resistance section connected between a common node and the first differential pair of PMOS transistors, wherein nodes between the first differential pair of PMOS transistors and the first load resistance section serve as an output terminal and an inversion output terminal; and a second amplifying circuit comprising: a second differential pair of NMOS transistors configured to receive the first and second input voltages; a second current source connected between the common node and the second differential pair of NMOS transistors; and a second load resistance section connected between the supply voltage and the second differential pair of NMOS transistors, wherein nodes between the second differential pair of NMOS transistors and the second load resistance section are respectively connected to the output terminal and the inversion output terminal. ### Claim 2 (depends on 1) The differential receiver of claim 1, further comprising a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is configured to provide a first bias voltage to the first amplifying circuit, and the second adjustment circuit is configured provide a second bias voltage to the second amplifying circuit. ### Claim 3 (depends on 2) The differential receiver of claim 2, wherein the first adjustment circuit and the second adjustment circuit receive an adjustable voltage, and the voltages of the output terminal and the inversion output terminal are adjusted by controlling the value of the adjustable voltage. ### Claim 4 (depends on 2) The differential receiver of claim 2, wherein the first adjustment circuit comprises: a first PMOS transistor having a source connected to the supply voltage, and having a gate configured to receive the first bias voltage; a second PMOS transistor having a source connected to a drain of the first PMOS transistor, and having a gate configured to receive the first input voltage; a load device having a first terminal connected to a drain of the second PMOS transistor and a second terminal connected to the common node; and an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the first terminal of the load device, and an output terminal connected to the gate of the first PMOS transistor. ### Claim 5 (depends on 2) The differential receiver of claim 2, wherein the second adjustment circuit comprises: a load device having a first terminal connected to the supply voltage source; a first NMOS transistor having a drain connected to a second terminal of the load device, and having a gate configured to receive the first input voltage; a second NMOS transistor having a drain connected to a source of the first NMOS transistor, having a gate configured to receive the second bias voltage, and having a source connected to the common node; and an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the second terminal of the load device, and an output terminal connected to the gate of the second PMOS transistor. ### Claim 6 (depends on 4) The differential receiver of claim 4, wherein the first load resistance section comprises two load devices which are connected between the common node and the first differential pair of PMOS transistors, and the voltages of the output terminal and the inversion output terminal are adjusted by selecting the value of the two load device and the load device of the first adjustment circuit. ### Claim 7 (depends on 5) The differential receiver of claim 5, wherein the second load resistance section comprises two load devices which are connected between the supply voltage source and the second differential pair of NMOS transistors, and the voltages of the output terminal and the inversion output terminal are adjusted by selecting the value of the two load device and the load device of the second adjustment circuit. ### Claim 8 (depends on 4) The differential receiver of claim 4, wherein the first current source comprises a third PMOS transistor having a source connected to the supply voltage source, a gate connected to the first bias voltage, and a drain connected to the first differential pair of PMOS transistors, and the voltages of the output terminal and the inversion output terminal are adjusted by selecting the size of the third PMOS transistor and that of the first PMOS transistor of the first adjustment circuit. ### Claim 9 (depends on 8) The differential receiver of claim 8, wherein the first load resistance section comprises two load devices which are connected between the common node and the first differential pair of PMOS transistors, the third PMOS transistor has a gate length that is the same as the gate length of the first PMOS transistor and a gate width that is twice the gate width of the first PMOS transistor, and the value of the two load device and the load device of the first adjustment circuit are the same. ### Claim 10 (depends on 5) The differential receiver of claim 5, wherein the second current source comprises a third NMOS transistor having a source connected to the common node, a gate connected to the second bias voltage, and a drain connected to the second differential pair of NMOS transistors, and the voltages of the output terminal and the inversion output terminal are adjusted by selecting the size of the third NMOS transistor and the second NMOS transistor of the second adjustment circuit. ### Claim 11 (depends on 10) The differential receiver of claim 10, wherein the second load resistance section comprises two load devices which are connected between the supply voltage source and the second differential pair of NMOS transistors, the third NMOS transistor has a gate length that is the same as the gate length of the second NMOS transistor and a gate width that is twice the gate width of the second NMOS transistor, and the value of the two load device and the load device of the second adjustment circuit are the same. ### Claim 12 A differential receiver, comprising: a first amplifying circuit comprising: a first differential pair of PMOS transistors configured to receive first and second input voltages; a first current source connected between a supply voltage source and the first differential pair of PMOS transistors; a first load resistance section having an output terminal and an inversion output terminal both connected between a common node and the first differential pair of PMOS transistors; a second amplifying circuit comprising: a second differential pair of NMOS transistors configured to receive the first and second input voltages; a second current source connected between the common node and the second differential pair of NMOS transistors; and a second load resistance section having the output terminal and the inversion output terminal both connected between the supply voltage and the second differential pair of NMOS transistors; and a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is configured to provide a first bias voltage to the first amplifying circuit, and the second adjustment circuit is configured provide a second bias voltage to the second amplifying circuit; wherein the first adjustment circuit comprises: a first PMOS transistor having a source connected to the supply voltage, and having a gate configured to receive the first bias voltage; a second PMOS transistor having a source connected to a drain of the first PMOS transistor, and having a gate configured to receive the first input voltage; a load device having a first terminal connected to a drain of the second PMOS transistor and a second terminal connected to the common node; and an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the first terminal of the load device, and an output terminal connected to the gate of the first PMOS transistor. ### Claim 13 A differential receiver, comprising: a first amplifying circuit comprising: a first differential pair of PMOS transistors configured to receive first and second input voltages; a first current source connected between a supply voltage source and the first differential pair of PMOS transistors; a first load resistance section having an output terminal and an inversion output terminal both connected between a common node and the first differential pair of PMOS transistors; a second amplifying circuit comprising: a second differential pair of NMOS transistors configured to receive the first and second input voltages; a second current source connected between the common node and the second differential pair of NMOS transistors; and a second load resistance section having the output terminal and the inversion output terminal both connected between the supply voltage and the second differential pair of NMOS transistors; and a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is configured to provide a first bias voltage to the first amplifying circuit, and the second adjustment circuit is configured provide a second bias voltage to the second amplifying circuit; wherein the second adjustment circuit comprises: a load device having a first terminal connected to the supply voltage source; a first NMOS transistor having a drain connected to a second terminal of the load device, and having a gate configured to receive the first input voltage; a second NMOS transistor having a drain connected to a source of the first NMOS transistor, having a gate configured to receive the second bias voltage, and having a source connected to the common node; and an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the second terminal of the load device, and an output terminal connected to the gate of the second PMOS transistor.