Duty cycle correction circuit of semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorHye Young Lee
Life of this patent
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Abstract
A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.
Claims43
A duty cycle correction circuit of a semiconductor memory apparatus, comprising:
- a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock;
- a duty detection unit configured to detect a duty of the duty corrected clock and output a first duty detection signal;
- and
- a duty correction code generation unit configured to generate the duty correction codes based on the first duty detection signal.
A duty cycle correction circuit of a semiconductor memory apparatus, comprising:
- a duty detection unit configured to detect a duty of a duty corrected clock and enable a first duty detection signal or a second duty detection signal;
- a duty correction code generation unit configured to increase and decrease a code value of duty correction codes in response to the first and second duty detection signals;
- and
- a duty correction unit configured to generate a delayed clock by delaying a clock, transfer a first pull-up driving force and a first pull-down driving force for determining a voltage level of a common node to the common node in response to the clock and the duty correction codes, transfer a second pull-up driving force and a second pull-down driving force for determining a voltage level of the common node to the common node in response to the delayed clock and the duty correction codes, and generate the duty corrected clock by driving a voltage of the common node.
A duty cycle correction circuit of a semiconductor memory apparatus, comprising:
- a duty correction range setting section configured to delay a clock and generate a delayed clock;
- a common node voltage determination section configured to determine a voltage level of a common node in response to one of a pull-up driving force and a pull-down driving force when phases of the clock and the delayed clock are the same with each other, and determine the voltage level of the common node in response to both the pull-up driving force and the pull-down driving force according to duty correction codes when the phases of the clock and the delayed clock are different from each other;
- and
- a driver configured to drive the voltage level of the common node and output a duty corrected clock.
Dependencies are inferred from the claim text.