Wake-up circuit and an on board unit including the same, a filter, methods for frequency detection and filtering

A filter for digital signals, comprising:

• a control signal generation circuit comprising,
• a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency of the digital signal;
• a first comparison circuit and a second comparison circuit both coupled to an output end of the pulse generator and configured to receive the pulse sequence signal;
• the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal based on the comparison;
• the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal based on the comparison;
• and
• a regeneration circuit configured to, based on the first control signal and the second control signal, generate an output signal with the frequency of the digital signal if the frequency of the digital signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein,
• the first comparison circuit comprises a first p-type MOSFET, a first capacitor and a first load, wherein a gate of the first p-type MOSFET is connected to the output end of the pulse generator, a drain of the first p-type MOSFET is connected to a negative terminal of the first capacitor to form a first common terminal, a source of the first p-type MOSFET is connected to a positive terminal of the first capacitor to form a second common terminal, the first common terminal is connected to one end of the first load and the second common terminal is connected to a positive voltage power source, the other end of the first load is grounded;
• the second comparison circuit comprises a second p-type MOSFET, a second capacitor and a second load, wherein a gate of the second p-type MOSFET is connected to the output end of the pulse generator, a drain of the second p-type MOSFET is connected to a negative terminal of the second capacitor to form a third common terminal, a source of the second p-type MOSFET is connected to a positive terminal of the second capacitor to form a fourth common terminal, the third common terminal is connected to one end of the second load and the fourth common terminal is connected to the positive voltage power supply, the other end of the second load is grounded.

A filter for digital signals, comprising:

• a control signal generation circuit comprising,
• a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency of the digital signal;
• a first comparison circuit and a second comparison circuit both coupled to an output end of the pulse generator and configured to receive the pulse sequence signal;
• the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal based on the comparison;
• the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal based on the comparison;
• and
• a regeneration circuit configured to, based on the first control signal and the second control signal, generate an output signal with the frequency of the digital signal if the frequency of the digital signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein,
• the first comparison circuit further comprises a first inverter and a second inverter, an input end of the first inverter is connected to the first common terminal, an output end of the first inverter is connected to an input end of the second inverter, the first control signal is outputted by the second inverter;
• the second comparison circuit further comprises a third inverter and a fourth inverter, an input end of the third inverter is connected to the third common terminal, an output end of the third inverter is connected to an input end of the fourth inverter, the second control signal is outputted by the fourth inverter.

A filter for digital signals, comprising:

• a control signal generation circuit comprising,
• a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency of the digital signal;
• a first comparison circuit and a second comparison circuit both coupled to an output end of the pulse generator and configured to receive the pulse sequence signal;
• the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal based on the comparison;
• the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal based on the comparison;
• and
• a regeneration circuit configured to, based on the first control signal and the second control signal, generate an output signal with the frequency of the digital signal if the frequency of the digital signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein the regeneration circuit comprises a first D-type flip-flop, a second D-type flip-flop and an AND gate, the first and second D-type flip-flops respectively comprise a D input end, a clock signal input end, a reset end and an output end,
• the D input end of the first D-type flip-flop is connected to the positive voltage power supply, the clock signal input end of the first D-type flip-flop is connected to an output end of the first comparison circuit and configured to receive the first control signal, the reset end of the first D-type flip-flop is connected to the output end of the second comparison circuit and configured to receive the second control signal, the output end of the first D-type flip-flop is connected to the D input end of the second D-type flip-flop, and
• the clock signal input end of the second D-type flip-flop is connected to the output end of the first comparison circuit and configured to receive the first control signal, the reset end of the second D-type flip-flop is connected to the output end of the second comparison circuit and configured to receive the second control signal, the output end of the second D-type flip-flop is connected to an input end of the AND gate,
• another input end of the AND gate is connected to the output end of the first comparison circuit and configured to receive the first control signal, an output end of the AND gate is taken as an output end of the regeneration circuit.

A method in a wake-up circuit, comprising:

• a. generating a pulse sequence signal with a frequency of a digital signal;
• b. comparing the frequency of the pulse sequence signal with a first threshold frequency, and generating a first control signal based on the comparison;
• c. comparing the frequency of the pulse sequence signal with a second threshold frequency, and generating a second control signal based on the comparison;
• d. generating, based on the first control signal and the second control signal, a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein the step b further comprises,
• comparing the frequency of the pulse sequence signal with the first threshold frequency and generating the first control signal based on the comparison by using a first comparison circuit, the first comparison circuit including,
• a first p-type MOSFET, a first capacitor and a first load, wherein a gate of the first p-type MOSFET is connected to the output end of the pulse generator, a drain of the first p-type MOSFET is connected to a negative terminal of the first capacitor to form a first common terminal, a source of the first p-type MOSFET is connected to a positive terminal of the first capacitor to form a second common terminal, the first common terminal is connected to one end of the first load and the second common terminal is connected to a positive voltage power source, the other end of the first load is grounded;
• the step c further comprises,
• comparing the frequency of the pulse sequence signal with the second threshold frequency and generating the second control signal based on the comparison by using a second comparison circuit, the second comparison circuit including,
• a second p-type MOSFET, a second capacitor and a second load, wherein a gate of the second p-type MOSFET is connected to an output end of the pulse generator, a drain of the second p-type MOSFET is connected to a negative terminal of the second capacitor to form a third common terminal, a source of the second p-type MOSFET is connected to a positive terminal of the second capacitor to form a fourth common terminal, the third common terminal is connected to one end of the second load and the fourth common terminal is connected to the positive voltage power source, the other end of the second load is grounded.

A method, comprising:

• e. generating a pulse sequence signal with a frequency of a digital signal;
• f. comparing the frequency of the pulse sequence signal with a first threshold frequency to generate a first control signal;
• g. comparing the frequency of the pulse sequence signal with a second threshold frequency to generate a second control signal;
• h. generating, based on the first control signal and the second control signal, an output signal with the frequency of the pulse sequence signal if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.
• wherein the step f further comprises,
• comparing the frequency of the pulse sequence signal with a first threshold frequency to generate a first control signal by using a first comparison circuit,
• wherein the first comparison circuit comprises a first p-type MOSFET, a first capacitor and a first load, wherein a gate of the first p-type MOSFET is connected to the output end of the pulse generator, a drain of the first p-type MOSFET is connected to a negative terminal of the first capacitor to form a first common terminal, a source of the first p-type MOSFET is connected to a positive terminal of the first capacitor to form a second common terminal, the first common terminal is connected to one end of the first load and the second common terminal is connected to a positive voltage power source, the other end of the first load is grounded;
• the step g further comprises,
• comparing the frequency of the pulse sequence signal with a second threshold frequency to generate a second control signal by using a second comparison circuit,
• wherein the second comparison circuit comprises a second p-type MOSFET, a second capacitor and a second load, wherein a gate of the second p-type MOSFET is connected to the output end of the pulse generator, a drain of the second p-type MOSFET is connected to a negative terminal of the second capacitor to form a third common terminal, a source of the second p-type MOSFET is connected to a positive terminal of the second capacitor to form a fourth common terminal, the third common terminal is connected to one end of the second load and the fourth common terminal is connected to the positive voltage power supply, the other end of the second load is grounded.

A method, comprising:

• e. generating a pulse sequence signal with a frequency of a digital signal;
• f. comparing the frequency of the pulse sequence signal with a first threshold frequency to generate a first control signal;
• g. comparing the frequency of the pulse sequence signal with a second threshold frequency to generate a second control signal;
• h. generating, based on the first control signal and the second control signal, an output signal with the frequency of the pulse sequence signal if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein,
• the first comparison circuit further comprises a first inverter and a second inverter, an input end of the first inverter is connected to the first common terminal, an output end of the first inverter is connected to an input end of the second inverter, the first control signal is outputted by the second inverter;
• the second comparison circuit further comprises a third inverter and a fourth inverter, an input end of the third inverter is connected to the third common terminal, an output end of the third inverter is connected to an input end of the fourth inverter, the second control signal is outputted by the fourth inverter.

A method, comprising:

• e. generating a pulse sequence signal with a frequency of a digital signal;
• f. comparing the frequency of the pulse sequence signal with a first threshold frequency to generate a first control signal;
• g. comparing the frequency of the pulse sequence signal with a second threshold frequency to generate a second control signal;
• h. generating, based on the first control signal and the second control signal, an output signal with the frequency of the pulse sequence signal if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies;
• wherein the step h further comprises,
• generating, based on the first control signal and the second control signal and by using a regeneration circuit, an output signal with the frequency of the pulse sequence signal if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies,
• wherein the regeneration circuit comprises a first D-type flip-flop, a second D-type flip-flop and an AND gate, the first and second D-type flip-flops respectively comprise a D input end, a clock signal input end, a reset end and an output end,
• the D input end of the first D-type flip-flop is connected to the positive voltage power supply, the clock signal input end of the first D-type flip-flop is connected to an output end of the first comparison circuit and configured to receive the first control signal, the reset end of the first D-type flip-flop is connected to the output end of the second comparison circuit and configured to receive the second control signal, the output end of the first D-type flip-flop is connected to the D input end of the second D-type flip-flop, and
• the clock signal input end of the second D-type flip-flop is connected to the output end of the first comparison circuit and configured to receive the first control signal, the reset end of the second D-type flip-flop is connected to the output end of the second comparison circuit and configured to receive the second control signal, the output end of the second D-type flip-flop is connected to an input end of the AND gate;
• another input end of the AND gate is connected to the output end of the first comparison circuit and configured to receive the first control signal, an output end of the AND gate is taken as an output end of the regeneration circuit.