Data transmission system and method

A driver for differentially transmitting data over a data bus having Ndata lines, the driver comprising:

• a plurality of driver cells (DO, . . . , DN) for receiving a first signal, a second signal, and an ordered set of N input signals (B0, . . . , BN−1) comprising data, the plurality of driver cells comprising:
• a first driver cell (DO) for receiving over a first input of DO the first signal and for receiving over a second input of DO a first input signal (BO), and for generating over an output of DO a first a 3-level transmission signal (SO) from a difference between BO and the first signal, DO having an impedance substantially matching the impedance of a first one of the N+1 data lines;
• an (N+1)th driver cell (DN) for receiving over a first input of DN an Nth input signal (BN−1)) and for receiving over a second input of DN the second signal, and for generating over an output of DN an (N+1)th 3-level transmission signal (SN) from a difference between BN−1 and the second signal, DN having an impedance substantially matching the impedance of a (N+1)th one of the (N+1) data lines;
• and
• N−1 driver cells Dj wherein j is an index with 1≦j≦N−1, each jth driver cell (Dj) of which is for receiving over a first input of Dj a (j−1)th input signal (Bj) and for receiving over a second input of Dj a jth input signal (Bj), and for generating a (j+1)th 3-level transmission signal (Sj) from a difference between Bj and Bj−1, the N−1 driver cells each having an impedance substantially matching the impedance of a respective one of N−1 of the (N+1) data lines,
• wherein the first signal and the second signal comprise an (N+2)th input signal (BN) comprising data.

A data transmission system for differentially transmitting data across a data bus of Ndata lines, said system comprising:

• a driver for receiving a first signal, a second signal, and an ordered set of N input signals (B0, . . . , BN−1) comprising data, wherein said driver is coupled to a first end of said data bus and is for transmitting the transmission signals from said first end of said data bus;
• and
• a receiver coupled to a second end of said data bus for receiving said transmission signals at said second end of said data bus;
• wherein said driver comprises:
• N+1 driver cells (DO, . . . , DN) comprising:
• a first driver cell (DO) for receiving over a first input of DO the first signal and for receiving over a second input of DO a first input signal (BO), and for generating over an output of DO a first 3-level transmission signal (SO) from a difference between BO and the first signal, DO having an impedance substantially matching the impedance of a first one of the N+1 data lines;
• an (N+1)th driver cell (DN) for receiving over a first input of DN an Nth input signal (BN−1) and for receiving over a second input of DN the second signal, and for generating over an output of DN an (N+1)th 3-level transmission signal (SN) from a difference between BN−1 and the second signal, DN having an impedance substantially matching the impedance of a (N+1)th one of the (N+1) data lines;
• and,
• N−1 driver cells Dj wherein j is an index with 1≦j≦N−1, each jth driver cell (Dj) of which is for receiving over a first input of Dj a (j−1)th input signal (Bj) and for receiving over a second input of Dj a jth input signal (Bj), and for generating a (j+1)th 3-level transmission signal (Sj) from a difference between Bj and Bj−1, the N−1 driver cells each having an impedance substantially matching the impedance of a respective one of N−1 of the (N+1) data lines;
• wherein each driver cell in generating each 3-level transmission signal generates a reference signal “0(Z)” in a case where a signal received over the first input of the driver cell is equal to a signal received over the second input of the driver cell;
• and,
• where said receiver comprises:
• N receiver cells (RX0, . . . , RXN−1) each ith receiver cell (RXi) of which is for receiving over a first input of RXi an ith transmission signal (Si), for receiving over a second input of RXi an (i+1)th transmission signal (Si+1), and for generating an ith direct output (DBITi) which equals:
• 1 in a case where Si+1 is less than Si, 0 in a case where Si+1 is greater than Si, and a high impedance stare “HZ” in a case where Si+1 equals Si;
• and for generating an ith indirect output (INDBITi) which equals:
• 0 in a case where Si+1 is less than S, 0 in a case where Si+1 is greater than Si, and 1 in a case where Si+1 equals Si;
• and
• N restore cells (RO, . . . , RN−1) comprising:
• a first restore cell (R0), for receiving over a first input of R0 a first direct bit (DBIT0), and over a second input of Ro a first indirect bit (INDBIT0), and for generating a first output bit (OUT0) of R0 which equals DBIT0 when INDBIT0 equals 0 and is coupled to a third signal when INDBIT0 equals 1;
• an Nth restore cell (RN−1), for receiving over a first input of RN−1 an Nth direct bit (DBITN−1), and over a second input of RN−1 an Nth indirect bit (INDBITN−1), and for generating an Nth output bit (OUTN−1) of RN−1 which equals DBITN−1 when INDBITN−1 equals 0 and is coupled to a fourth signal when INDBITN−1 equals 1;
• and
• N−2 restore cells (R1, . . . , RN−2) each kth restore cell (Rk) of which is for receiving over a first input of Rk a kth direct bit (DBITk), and over a second input of Rk, a kth indirect bit (INDBITk), and for generating a kth output bit (OUTk) of Rk which equals DBITk when INDBITk equals 0, and for generating a kth output bit OUTk of Rk which equals an output OUTk+1 of the (k+1)th recover cell Rk+1 and an output OUTk−1 of the (k−1)th recover cell Rk−1 when INDBITk equals 1.

A data transmission system for differentially transmitting data across a data bus of N+1 data lines, said system comprising:

• a driver for receiving a first signal, a second signal, and an ordered set of N input signals (B0, . . . , BN−1) comprising data, wherein said driver is coupled to a first end of said data bus and is for transmitting the transmission signals from said first end of said data bus;
• and
• a receiver coupled to a second end of said data bus for receiving said transmission signals at said second end of said data bus;
• wherein said driver comprises:
• N+1 driver cells (D0, . . . , DN) comprising:
• a first driver cells (D0) for receiving over a first input of D0 the first signal and for receiving over a second input of D0 a first input signal (B0), and for generating over an output of D0 a first 3-level transmission signal (S0) from a difference between B0 and the first signal, D0 having an impedance substantially matching the impedance of a first one of the N+1 data lines;
• an (N+1)th driver cell (DN) for receiving over a first input of DN an Nth input signal (BN−1) and for receiving over a second input of DN the second signal, an d for generating over an output of DN an (N+1)th 3-level transmission signal (SN ) from a difference between BN−1 and the second signal, DN having an impedance substantially matching the impedance of a (N+1)th one of the (N+1) data lines;
• and,
• N−1 driver cells Dj wherein j is an index with 1≦j≦N−1, each jth driver cell (Dj) of which is for receiving over a first input of Dj a (j−1)th input signal (Bj−1) and for receiving over a second input of Dj a jth input signal (Bj), and for generating a (j+1)th 3-level transmission signal (Sj) from a difference between Bj and Bj−1, the N−1 driver cells each having an impedance substantially matching the impedance of a respective one of N−1 of the (N+1) data lines;
• wherein each driver cell in generating each 3-level transmission signal generates a reference signal “0(Z)” in a case where a signal received over the first input of the driver cell is equal to a signal received over the second input of the driver cell;
• and,
• wherein the first signal comprises a digital voltage V0 and the second signal comprises an (N+1)th input signal (BN), said receiver comprising:
• N receiver cells (RX0, . . . , RXN−1), each ith receiver cell (RXi) of which is for receiving over a first input of RXi an ith transmission signal (Si), for receiving over a second input of RXi an (i+1)th transmission signal (Si+1), and for generating an ith direct output (DBITi) which equals:
• 1in a case where Si+1 is less than Si, 0 in a case where Si+1 is greater than Si, and a high impedance state “HZ” in a case where Si+1 equals Si;
• and for generating an ith indirect output (INDBITi) which equals:
• 0 in a case where Si+1 is less than Si, 0 in a case where Si+1 is greater than Si, and 1 in a case where Si+1 equals Si;
• and
• N restore cells (R0, . . . , RN−1) comprising:
• a first restore cell (R0), for receiving over a first input of R0 a first direct bit (DBIT0), and over a second input of R0 a first indirect bit (INDBIT0), and for generating a first output (OUT0) of R0 which equals DBIT0 when INDBIT0 equals 0 and equal said V0 when INDBIT0 equals 1;
• an Nth restore cells (RN−1), for receiving over a first input of RN−1 an Nth direct bit (DBITN−1), and over a second input of RN−1 an Nth indirect bit (INDBITN−1), and for generating an Nth output bit (OUTN−1) of RN−1 which equals DBITN−1 when INDBITN−1 equals 1;
• and
• N−2 restore cells (R1, . . . , RN−2), each kth restore cell (Rk) of which is for receiving over a first input of Rk a kth direct bit (DBITk), and over a second input of Rk, a kth indirect bit (INDBITk), and for generating a kth output bit (OUTk) of Rk which equals DBITk when INDBITk equals 0, and for generating a kth output bit OUTk of Rk which equals an output OUTk+1 of the (k+1)th recover cell Rk+1 and an output bit OUTk−1 of the (k−1)th recover cell Rk−1;
• another receiver cell (RX′) for receiving over a first input of RXi the transmission signal (SN−1), for receiving over a second input of RX′ the transmission signal (SN), and for generating an N+1th indirect output (INDBITN+1) which equals:
• 0 in a case where one of SN and SN+1 equals +1 and the other equals −1, and 1 otherwise;
• and
• an other restore cell (R′) for receiving over a first input of R′ said Nth indirect bit (INDBITN−1), over a second input of R′ said N+1th indirect output (INDBITN), and over an other input the output bit of the (N−2)th restore cell (RN−3), for generating an N+1th output bit (OUTN) of R′ based on the indirect bit (INDBITN−1), the indirect bit INDBITN, and the output bit of the at least one of the restore cells.

A data transmission system for differentially transmitting data across a data bus of N+1 data lines, said system comprising:

• a driver for receiving a first signal, a second signal, and an ordered set of N input signals (B0, . . . , BN−1) comprising data, wherein said driver is coupled to a first end of said data bus and is for transmitting the transmission signals from said first end of said data bus;
• a receiver coupled to a second end of said data bus for receiving said transmission signals at said second end of said data bus;
• wherein said driver comprises:
• N+1 driver cells (D0, . . . , DN) comprising:
• a first driver cell (D0) for receiving over a first input of D0 the first signal and for receiving over a second input of D0 a first input signal (B0), and for generating over an output of D0 a first 3-level transmission signal (S0 from a difference between B0 and the first signal, D0 having an impedance substantially matching the impedance of a first one of the N+1 data lines;
• an (N+1)the driver cell (DN) for receiving over a first input of DN an Nth input signal (BN−1) and for receiving over a second input of DN the second signal, and for generating over an output of DN an (N+1)th 3-level transmission signal (SN) from a difference between BN−1 and the second signal, DN having an impedance substantially matching the impedance of a (N+1)th one of the (N+1) data lines;
• and,
• N−1 driver cells Dj wherein j is an index with 1≦j≦N−1, each jth driver cell (Dj) of which is for receiving over a first input of Dj a (j−1)th input signal (Bj−1) and for receiving over a second input of Dj a jth input signal (Bj), and for generating a (j+1)th 3-level transmission signal (Sj) from a difference between Bj and Bj−1, the N−1 driver cells each having an impedance substantially matching the impedance of a respective one of N−1 of the (N+1) data lines;
• and,
• an encoder for predicting 3-level differentially generated transmission signals resulting from input data bits of the data, generating predicted transmission signals, analyzing the predicted transmission signals, choosing a predetermined polarity reversal combination and an associated formatting value F;
• encoding the data bits by reversing polarity of the data bits according to the predetermined polarity reversal combination, generating encoded bits;
• and transmitting said encoded bits and bits of F to said driver wherein said encoded bits and bits of F compose said ordered set of N input signals;
• and
• a decoder coupled to said receiver:
• for receiving said encoded bits and F recovered by said receiver;
• for determining the determined polarity reversal combination associated with F;
• for decoding the encoded bits by reversing polarity of the encoded bits according said predetermined polarity reversal combination, generating decoded bits, and for outputting the decoded bits.

a method of differentially transmitting data across a data bus, the method comprising:

• predicting 3-level differentially generated transmission signals resulting from input data bits of the data;
• analyzing the predicted transmission signals;
• choosing a predetermined polarity reversal combination and an associated formatting value F from the analyzing the predicted transmission signals;
• encoding the data bits by reversing polarity of the data bits according to the predetermined polarity reversal combination to generate encoded bits;
• differentially generating 3-level transmission signals from the encoded bits and F, wherein F is for use in decoding said encoded bits;
• and
• transmitting the differentially generated 3-level transmission signals from a first end of said data bus.

A method of differentially transmitting data on a data bus having N+1 data lines comprising:

• for a first input signal (B0), generating a first 3-level transmission signal (S0) from a difference between B0 and a first other signal;
• for an Nth input signal (BN−1), generating an (N+1)th 3-level transmission signal (SN) from a difference between BN−1 and a second other signal;
• and
• for each jth input signal Bj of N−1 input signals (B1, . . . , BN−2) wherein j is an index with 1≦j≦N−1, generating a jth 3-level transmission signal (Sj) from a difference between Bj and Bj−1, and wherein each 3-level signal is generated using a driver cell having an impedance substantially matching the impedance of a respective one of the N+1 data lines,
• wherein generating each transmission signal comprises generating a reference signal “0(Z)” in a case where a respective difference results in a 0;
• and,
• generating for each ith 3-level transmission signal (Si) other than the first 3-level transmission signal (S0), an ith direct output (DBITi) which equals:
• 1 in a case where Si is less than an (i−1)th transmission signal (Si−1), 0 in a case where Si is greater than Si−t, and high impedance state “HZ” in a case where Si equals Si−1;
• and an ith indirect output (INDBITi) which equals:
• 0 in a case where Si is less than Si−1, 0 in a case where Si is greater than Si−1, and 1 in a case where Si equals Si−1;
• for each kth indirect output INDBITk equalling 0 generating a kth output bit (OUTk) which equals the kth direct output (DBITk);
• for each kth indirect output (IDBITi) other than a first indirect output (INDBIT0) and other than an Nth indirect output (INDBITN−1), which equals 1, generating a kth output bit OUTk equal to a (k−1)th output bit (OUTk−1) and equal to a (k+1)th output bit (OUTk+1);
• for the first indirect output INDBIT0 equaling 1, generating a first output bit OUT0 equal to a third signal;
• and
• for the Nth indirect output INDBITN−1 equaling 1, generating an Nth output bit OUTN equal to a fourth signal.

A driver for differentially transmitting data over a data bus having N+1 data lines, the driver comprising:

• a plurality of driver cells (D0, . . . , DN) for receiving a first signal, a second signal, and an ordered set of N input signals (B0, . . . , BN−2) comprising data, the plurality of driver cells comprising:
• a first driver cell (D0) for receiving over a first input of D0 the first signal and for receiving over a second input of D0 a first input signal (B0), and for generating over an output of D0 a first a 3-level transmission signal (S0) from a difference between B0 and the first signal;
• an (N+1)th driver cell (DN) for receiving over a first input of DN an Nth input signal (BN−1) and for receiving over a second input of DN the second signal, and for generating over an output of DN an (N+1)th 3-level transmission signal (SN) from a difference between BN−1 and the second signal;
• and
• N−1 driver cells Dj wherein j is an index with 1≦j≦N−1, each jth driver cell (Dj) of which is for receiving over a first input of Dj a (j−1)th input signal (Bj−1) and for receiving over a second input of Dj a jth input signal (Bj), and for generating a (j+1)th 3-level transmission signal (Sj) from a difference between Bj and Bj−1,
• wherein at least one of the first signal and the second signals comprise(s) data.