Method and apparatus for dynamic memory termination
AssigneeIntel Corporation
InventorsJames A. McCall, Kuljit S. Bains
Life of this patent
Estimating the term…
Abstract
Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
Claims36
A method comprising:
- setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory;
- assigning the first termination impedance value setting as a default value setting to the termination unit when the memory is not being accessed;
- and
- switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level, wherein the first and second termination impedance values are finite values, wherein the first impedance value is greater than the second impedance value, and wherein the first and second termination value settings are stored in a register of a memory controller coupled to the memory.
An apparatus comprising:
- an interface operable to access a memory having a register with a first termination impedance value setting for a termination unit of an input-output (I/O) interface of the memory;
- a first logic unit operable to assign the first termination impedance value setting as a default value setting to the termination unit when the memory is not being accessed;
- and
- a second logic unit operable to switch from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level, wherein the first and second termination impedance values are finite values, wherein the first impedance value is greater than the second impedance value, and wherein the first and second termination value settings are stored in a register of a memory controller coupled to the memory.
A system comprising:
- a memory having a register operable to store a first termination impedance value setting for a termination unit of an input-output (I/O) interface of the memory;
- and
- a memory controller coupled to the memory and operable to adjust the termination impedance setting of the I/O interface of the memory, the memory controller comprising:
- a first logic unit operable to assign the first termination impedance value setting as a default value setting to the termination unit when the memory is not being accessed;
- a second logic unit operable to switch from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level, wherein the first and second termination impedance values are finite values, and wherein the first impedance value is greater than the second impedance value;
- and
- a register operable to store the first and second termination value settings.
Dependencies are inferred from the claim text.