# US 8,274,302 B2 · Wafer and test method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,274,302 B2
- Document ID: US8274302B2
- Status: Granted
- Kind: B2
- Application number: 12/609,365
- Filed: 2009-10-30
- Published: 2010-02-25
- Granted: 2012-09-25
- Earliest claimed: 2007-08-31
- Assignees: Himax Technologies Limited
- Inventors: Tzong-Yau Ku; Chien-Ru Chen; Chin-Tien Chang; Ying-Lieh Chen; Lin-Kai Bu
- Web page: https://patentgrep.com/patent/US8274302B2

## CPC

- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

## Claims

### Claim 1

A wafer test method, comprising:
selecting a first chip from a wafer to be tested to perform an HVS test; and
selecting a second chip from the wafer to be tested to perform a function test, wherein a period of the HVS test overlaps a period of the function test.

### Claim 2 (depends on 1)

The wafer test method as claimed in claim 1, wherein the first chip comprises a primary pad and a secondary pad connected in parallel with the primary pad, and the step of performing the HVS test comprises:
providing a high voltage electric energy to the first chip through the secondary pad, so as to perform the HVS test.

### Claim 3 (depends on 1)

The wafer test method as claimed in claim 1, wherein the first chip comprises a core circuit and a BIST circuit coupled to the core circuit, and the step of performing the HVS test comprises:
providing a high voltage electric energy to the core circuit; and
controlling the BIST circuit to provide test signals to the core circuit, so as to perform the HVS test.

### Claim 4 (depends on 3)

The wafer test method as claimed in claim 3, further comprising:
controlling the BIST circuit to provide a gamma voltage, a data initial pulse, a line latch line, and a polarity control signal to the core circuit, so as to perform the HVS test.

### Claim 5 (depends on 1)

The wafer test method as claimed in claim 1, wherein the second chip comprises a core circuit, and a BIST circuit coupled to the core circuit, and the step of performing the function test comprises:
controlling the BIST circuit to provide test signals to the core circuit, so as to perform the function test.

### Claim 6 (depends on 5)

The wafer test method as claimed in claim 5, further comprising:
controlling the BIST circuit to provide a gamma voltage, an input data, a data initial pulse, a line latch line, and a polarity control signal to the core circuit, so as to perform the function test.

### Claim 7 (depends on 1)

The wafer test method as claimed in claim 1, further comprising:
selecting a third chip from the wafer to be tested to perform the HVS test;
wherein the tests performed on the first chip, the second chip, and the third chip are performed simultaneously.