# US 8,274,205 B2 · System and method for limiting arc effects in field emitter arrays

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,274,205 B2
- Document ID: US8274205B2
- Status: Granted
- Kind: B2
- Application number: 11/567,095
- Filed: 2006-12-05
- Published: 2008-06-05
- Granted: 2012-09-25
- Earliest claimed: 2006-12-05
- Assignees: General Electric Company
- Inventors: Colin R. Wilson; Ji-Ung Lee
- Web page: https://patentgrep.com/patent/US8274205B2

## CPC

- H01J 1/3044: {Point emitters}
- H01J 35/065: {Field emission, photo emission or secondary emission cathodes}
- H01J 2235/068: Multi-cathode assembly
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)

## Abstract

The system and method provided herein for limiting the effects of arcing in field-type electron emitter arrays improves the robustness of such arrays. Field-type electron emitter arrays generally have a substrate, an insulator, and a gating electrode. By including a resistive substance in the gate of the emitter array, arcing events may be isolated to a single emitter such that the remaining emitters of an array can continue electron emission and/or the short circuit current of the arc can be limited.

## Claims

### Claim 1

A field emitter array comprising:
a substrate layer;
a gate layer having a plurality of openings formed therethrough;
a dielectric layer between the substrate layer and the gate layer, the dielectric layer having a number of cavities therein extending to the substrate layer;
a plurality of emitters, each emitter disposed on the substrate layer in a cavity of the dielectric layer and designed to emit electrons when an emission voltage is applied across the gate layer and the substrate layer; and
wherein the gate layer comprises a resistive layer and a conductive layer, said resistive layer having an electrical resistance to interrupt an arc path between the conductive layer and the emitter, wherein the resistive layer extends to the substrate layer and is between the conductive layer and the dielectric layer and the resistive layer is also between the conductive layer and the emitter disposed in the cavity.

### Claim 2 (depends on 1)

The field emitter array of claim 1 wherein the plurality of openings formed through the gate layer and the number of cavities of the dielectric layer substantially overlap.

### Claim 3 (depends on 1)

The field emitter array of claim 1 wherein the conductive layer is a metal grid formed on the resistive layer.

### Claim 4 (depends on 1)

The field emitter array of claim 1 wherein the resistive layer at least partially intervenes between the conductive layer and each of the plurality of emitters.

### Claim 5 (depends on 1)

The field emitter array of claim 1 wherein the gate layer is configured to maintain an electron emission voltage for a number of the plurality of emitters when one emitter is shorted.

### Claim 6 (depends on 1)

The field emitter array of claim 1 wherein the resistive layer is a semiconductor layer.

### Claim 7 (depends on 6)

The field emitter array of claim 6 wherein conductivity of the semiconductor layer is controlled by an amount of dopant, wherein the dopant is one of phosphorus (P) for an n-type semiconductor layer or boron (B) for a p-type semiconductor layer.

### Claim 8 (depends on 1)

The field emitter array of claim 1 wherein the resistive layer is positioned to at least partially intervene between the gate layer and the emitters.

### Claim 9 (depends on 1)

The field emitter array of claim 1 wherein the conductive layer is a grid pattern having a number of surrounding portions and a number of connecting portions, wherein there is a spaced distance between said emitters and said conductive layer such that a portion of the resistive layer intervenes an arc path from between the conductive layer and the emitter.

### Claim 10

An electron stream generator comprising:
an electron emitter positioned upon a substrate; and
a controller configured to selectively apply a potential across a gate layer and a substrate;
the gate layer positioned to create an electric field sufficient to cause electron emission from the emitter when the potential is applied thereto, and
the gate layer comprising a resistive layer and a conductive layer, the resistive layer extending to said substrate and intervening between the conductive layer and the emitter.

### Claim 11 (depends on 10)

The electron stream generator of claim 10 wherein the resistive layer is configured to limit short circuit arc current between the gate layer and the emitter.

### Claim 12 (depends on 10)

The electron stream generator of claim 10 wherein the gate layer is a metal lithographed grid.

### Claim 13 (depends on 10)

The electron stream generator of claim 10 wherein the resistive layer is configured to maintain operation of a number of other emitter elements when the given emitter element experiences arcing.

### Claim 14 (depends on 10)

The electron stream generator of claim 10 wherein the resistive layer is positioned to at least partially intervene between the gate layer and the given emitter element.