# US 8,274,163 B2 · Method and apparatus providing integrated circuit having redistribution layer with recessed connectors

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- Number: US 8,274,163 B2
- Document ID: US8274163B2
- Status: Granted
- Kind: B2
- Application number: 13/097,463
- Filed: 2011-04-29
- Published: 2011-08-18
- Granted: 2012-09-25
- Earliest claimed: 2007-03-27
- Assignees: Micron Technology, Inc.
- Inventors: David Pratt
- Web page: https://patentgrep.com/patent/US8274163B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.

## Claims

### Claim 1

A semiconductor die, comprising:
a substrate having a first side and a second side;
an integrated circuit formed on the second side of the substrate;
a stud arranged through the substrate and electrically coupling the integrated circuit to the first side of the substrate;
a trench arranged in the substrate around the stud and extending away from the stud;
a first dielectric layer arranged in the trench; and
a conductive layer arranged and wholly contained within the trench on the first dielectric layer, electrically coupling a first bond pad at the stud to a second bond pad remotely located from the stud, the first and second bond pads also being wholly contained within the trench.

### Claim 2 (depends on 1)

The semiconductor die of claim 1, further comprising a second dielectric layer arranged over the conductive layer and the first dielectric layer.

### Claim 3 (depends on 2)

The semiconductor die of claim 2, wherein a portion of the conductive layer arranged away from the stud is not covered by the second dielectric layer.

### Claim 4 (depends on 2)

The semiconductor die of claim 2, wherein the stud is not covered by the second dielectric layer.

### Claim 5 (depends on 1)

The semiconductor die of claim 1, further comprising a dielectric layer arranged around the through wafer interconnect stud.

### Claim 6 (depends on 1)

The semiconductor die of claim 1, further comprising a redistribution line electrically coupling the integrated circuit to the stud.

### Claim 7 (depends on 1)

The semiconductor die of claim 1, wherein the stud is substantially perpendicular to the plane of the substrate.

### Claim 8 (depends on 1)

The semiconductor die of claim 1, wherein the stud is surrounded by at least one dielectric layer.

### Claim 9 (depends on 1)

The semiconductor die of claim 1, wherein the conductive layer forms the first bond pad, the second bond pad, and a conductive trace between the first bond pad and the second bond pad.

### Claim 10 (depends on 1)

The semiconductor die of claim 1, wherein the conductive layer comprises at least one of aluminum, copper, an alloy of aluminum, and an alloy of copper.