Active area bonding compatible high current structures
AssigneeIntersil Americas Inc.
InventorsJohn T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
Life of this patent
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Abstract
A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
Claims22
A method of forming a semiconductor structure, the method comprising:
- forming at least one active device in a substrate;
- forming one or more intermediate metal layers between a top metal layer and the substrate;
- forming one or more insulation layers, the one or more insulation layers separating the one or more intermediate metal layers and the top metal layer;
- forming a passivation layer over the top metal layer;
- patterning the passivation layer to form a bond pad on the top metal layer, wherein the at least one active device is located directly under the bond pad;
- and
- wherein one of the one or more insulation layers is located adjacent to the top metal layer and has a thickness selected to resist cracking due to vertical and horizontal stresses on the semiconductor structure.
A method of forming a semiconductor structure, the method comprising:
- forming one or more intermediate metal layers above a substrate;
- forming one or more insulation layers, each of the one or more insulation layers formed above one of the one or more intermediate metal layers;
- forming a top metal layer above the one or more insulation layers, wherein the one or more insulation layers separate the one or more intermediate metal layers and the top metal layer from each other;
- and
- forming a passivation layer over the top metal layer;
- wherein one of the one or more insulation layers adjacent the top metal layer is formed to have a thickness that resists formation of cracks due to stresses caused by at least one of a bond wire attachment process or temperature excursions.
A method of forming a semiconductor structure, the method comprising:
- forming one or more intermediate metal layers between a top metal layer and a substrate;
- forming at least one active device in the substrate;
- forming a bond pad on the top metal layer, wherein the at least one active device is located directly under the bond pad;
- forming one or more insulation layers, the one or more insulation layers separating the one or more intermediate metal layers and the top metal layer;
- forming a segment of a single conductor line under the bond pad, the segment of the single conductor line formed from an intermediate metal layer adjacent to an insulation layer that is adjacent to the top metal layer;
- and
- patterning the segment of the single conductor line under the bond pad with gaps.
A semiconductor structure, the structure comprising:
- a top metal layer, the top metal layer including a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer,
- a bond pad formed on the top metal layer;
- a conductor below the top metal layer;
- and
- an insulation layer separating the conductor from the top metal layer;
- wherein the sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
Dependencies are inferred from the claim text.