A method of manufacturing a semiconductor device, comprising:
- forming a transistor on a semiconductor substrate;
- forming a first insulating film, covering the transistor, on the semiconductor substrate;
- forming a ferroelectric capacitor on the first insulating film, the ferroelectric capacitor being configured of a lower electrode, a ferroelectric film and an upper electrode;
- forming a second insulating film, covering the ferroelectric capacitor, on the first insulating film;
- planarizing an upper surface of the second insulating film;
- forming a first contact hole all at once after the planarizing, the first contact hole extending from an upper surface of the second insulating film, and reaching one of a plurality of impurity regions constituting the transistor;
- forming a plug by embedding a conductor in the first contact hole, the plug being electrically connected to the impurity region;
- forming a first hydrogen barrier layer on the second insulating film, the first hydrogen barrier layer being that which prevents hydrogen and moisture from entering a portion under the first hydrogen barrier layer;
- forming a third insulating film on the first hydrogen barrier layer;
- forming second contact holes which extend from an upper surface of the third insulating film, and which respectively reach the upper electrode and the lower electrode of the ferroelectric capacitor;
- performing a recovery annealing process on the ferroelectric capacitor;
- forming a third contact hole which extends from the upper surface of the third insulating film, and which reaches the plug;
- and
- forming interconnections on the third insulating film, two of the interconnections being electrically connected respectively to the upper electrode and the lower electrode of the ferroelectric capacitor through the second contact holes, and another one of the interconnections other than the two of the interconnections being electrically connected to the plug through the third contact hole.