# US 8,274,149 B2 · Semiconductor device package having a buffer structure and method of fabricating the same

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- Number: US 8,274,149 B2
- Document ID: US8274149B2
- Status: Granted
- Kind: B2
- Application number: 12/749,191
- Filed: 2010-03-29
- Published: 2011-09-29
- Granted: 2012-09-25
- Earliest claimed: 2010-03-29
- Assignees: Advanced Semiconductor Engineering, Inc.
- Inventors: Hsiao-Chuan Chang; Tsung-Yueh Tsai; Yi-Shao Lai; Ming-Hsiang Cheng
- Web page: https://patentgrep.com/patent/US8274149B2

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/348: {Top-view layouts, e.g. mirror arrays}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

## Claims

### Claim 1

A semiconductor device package, comprising:
a substrate having a cavity, a first surface and a second surface opposite to the first surface, wherein the cavity is extended from the first surface toward the second surface;
a buffer structure disposed in the cavity, wherein the buffer structure comprises a vesicant material;
two active chips mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface; and
a bridge chip disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the two active chips.

### Claim 2 (depends on 1)

The semiconductor device package according to claim 1, wherein the vesicant material is a thermosetting material.

### Claim 3 (depends on 1)

The semiconductor device package according to claim 1, wherein the buffer structure comprises a plurality of knobs.

### Claim 4 (depends on 1)

The semiconductor device package according to claim 1, further comprising two adhesion layers disposed between the active chips and the bridge chip respectively.

### Claim 5 (depends on 1)

The semiconductor device package according to claim 1, further comprising two adhesion layers disposed between the active chips and the first surface respectively.

### Claim 6 (depends on 1)

The semiconductor device package according to claim 1, further comprising a plurality of solder bumps disposed between the active chips and the first surface.

### Claim 7 (depends on 1)

The semiconductor device package according to claim 1, wherein the active chips each comprise a first signal pad disposed on the first active surface, the bridge chip comprises two second signal pads disposed on the second active surface and in accordance with the first signal pads for capacitively or inductively coupling to the first signal pads.

### Claim 8

A semiconductor device package, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a buffer structure disposed on the first surface;
two pillar sets disposed on two sides of the buffer structure respectively, wherein each pillar set has a plurality of pillars;
two active chips disposed on the pillar sets and electrically connected to the first surface, wherein the active chips both have a first active surface; and
a bridge chip disposed on the buffer structure and below the active chips, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the two active chips.

### Claim 9 (depends on 8)

The semiconductor device package according to claim 8, further comprising an underfill disposed between the pillar sets and the substrate.

### Claim 10 (depends on 8)

The semiconductor device package according to claim 8, wherein the buffer structure comprises a vesicant material.

### Claim 11 (depends on 10)

The semiconductor device package according to claim 10, wherein the vesicant material is a thermosetting material.

### Claim 12 (depends on 8)

The semiconductor device package according to claim 8, wherein the buffer structure comprises a plurality of knobs.

### Claim 13 (depends on 8)

The semiconductor device package according to claim 8, further comprising two adhesion layers disposed between the active chips and the bridge chip respectively.

### Claim 14 (depends on 8)

The semiconductor device package according to claim 8, wherein the active chips each comprise a first signal pad disposed on the first active surface, the bridge chip comprises two second signal pads disposed on the second active surface and in accordance with the first signal pads for capacitively or inductively coupling to the first signal pads.