Back to results
US 8,274,145 B2Granted
Semiconductor package system with patterned mask over thermal relief
AssigneeSTATS ChipPAC, Ltd.
InventorsLeocadio M. Alabin, Librado Gatbonton, Chiu Hsieh Ong, Beng Yee Teh, Antonio B. Dimaano, Jr.
Life of this patent
Estimating the term…
Abstract
A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
Claims20
A method for manufacturing a semiconductor package system comprising:
- providing a substrate having thermal relief pads thereon;
- depositing a mask on the substrate and the thermal relief pads;
- processing the mask with a pattern of holes, the substrate and only one of the thermal relief pads partially exposed from one of the holes;
- and
- mounting a semiconductor die over the thermal relief pads, the thermal relief pads directly under and within planar extents of the semiconductor die.
2 more elements
A method for manufacturing a semiconductor package system comprising:
- providing a substrate having thermal relief pads thereon;
- depositing a solder mask on the substrate and the thermal relief pads;
- processing the solder mask with a pattern of holes, the substrate and only one of the thermal relief pads partially exposed from one of the holes;
- and
- mounting a semiconductor die over the thermal relief pads, the thermal relief pads directly under and within planar extents of the semiconductor die.
2 more elements
A semiconductor package system comprising:
- a substrate having thermal relief pads thereon;
- a mask on the substrate and the thermal relief pads, the mask having a pattern of holes, the substrate and only one of the thermal relief pads partially exposed from one of the holes;
- and
- a semiconductor die over the thermal relief pads, the thermal relief pads directly under and within planar extents of the semiconductor die.
1 more element
Dependencies are inferred from the claim text.