US 8,274,119 B2Granted

Hybrid material accumulation mode GAA CMOSFET

AssigneeShanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

InventorsDeyuan Xiao, Xi Wang, Miao Zhang, Jing Chen, Zhongying Xue

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Abstract

A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.

Claims18

Dependent claims

A hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising:

a semiconductor substrate,
an NMOS region stacked up above the semiconductor substrate, having a second channel, and including a source region and a drain region located at two opposite ends of the second channel respectively thereof,
a PMOS region stacked up above the NMOS region, having a first channel, and including a source region and a drain region located at two opposite ends of the first channel respectively thereof,
a gate region surrounding two surfaces of the first channel and the second channel substantially,
a first buried oxide layer disposed between the PMOS region and the NMOS region other than the gate region, and
a second buried oxide layer disposed between the NMOS region and the semiconductor substrate other than the gate region,
wherein the first channel and the second channel each has a racetrack-shaped cross section having a rectangular central portion and two substantially semicircular end portions at the opposite ends of the rectangular central portion, the first channel is stacked up above the second channel and each of them is parallel to the semiconductor substrate, and the first channel is formed of p-type Ge and the second channel is formed of n-type Si.

4 more elements

A hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising:

a semiconductor substrate,
a PMOS region stacked up above the semiconductor substrate, having a first channel and including a source region and a drain region located at two opposite ends of the first channel respectively thereof,
an NMOS region stacked above the PMOS region, having a second channel and including a source region and a drain region located at two opposite ends of the second channel respectively thereof,
a gate region surrounding two surfaces of the first channel and the second channel substantially,
a first buried oxide layer disposed between the PMOS region and the NMOS region other than the gate region, and
a second buried oxide layer disposed between the PMOS region and the semiconductor substrate other than the gate region,
wherein the first channel and the second channel each has a racetrack-shaped cross section having a rectangular central portion and two substantially semicircular end portions at the opposite ends of the rectangular central portion, the first channel is stacked up above the second channel and each of them is parallel to the semiconductor substrate and the first channel is formed of p-type Ge and the second channel is formed of n-type Si.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/810,648Filed 11 Feb 2010
Priority: CN 2009 1 01997231 Dec 2009
Published: US 2011/0254100 A120 Oct 2011
Granted: 25 Sep 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 86/011
Manufacture or treatment: comprising FinFETs
H10D 30/504
Characterised by the stacked channels: wherein the stacked channels have different properties
H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile