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US 8,274,116 B2Granted
Control of threshold voltages in high-k metal gate stack and structures for CMOS devices
AssigneeInternational Business Machines Corporation
InventorsHemanth Jagannathan, Takashi Ando, Vijay Narayanan
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Abstract
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.
Claims3
A semiconductor structure comprising:
- an n-type field effect transistor having a first patterned material stack disposed on a semiconductor substrate;
- and
- a p-type field effect transistor having a second patterned material stack disposed on the semiconductor substrate, the first patterned material stack and the second patterned material stack, each comprising:
- a germanium (Ge) material layer formed on the semiconductor substrate;
- a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the Ge material layer;
- and
- a conductive electrode layer formed above the high-k dielectric layer, and
- wherein only the first patterned material stack additionally comprises a diffusion barrier layer formed between the high-k dielectric and the Ge material layer.
5 more elements
Dependencies are inferred from the claim text.