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US 8,274,110 B2Granted
Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
AssigneeMicron Technology, Inc.
InventorsGurtej Sandhu, John K. Zahurak, Jay Parks
Life of this patent
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Abstract
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
Claims26
A transistor structure comprising:
- a semiconductor material base;
- a semiconductor material mesa upstanding from said base;
- a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
- a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
- first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
- a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
- and
- a plurality of operative electrical devices respectively connected to each of said first silicide elements.
5 more elements
A transistor structure comprising:
- a semiconductor material base;
- a semiconductor material mesa upstanding from said base;
- a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
- a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
- first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
- a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
- a third silicide material element supported on said semiconductor material base at a second side of said mesa opposite said first side;
- and
- a second mesa sidewall gate structure provided on said second side of said mesa and comprising a gate insulator material and an overlying gate conductor, said second mesa sidewall gate structure being operative to control with said first mesa sidewall gate structure current flow between each of said first silicide material elements and said second material element and each of said first silicide material elements and said third silicide material element through said mesa;
- and
- a recess in the top surface of each mesa between an adjacent pair of first silicide material elements.
8 more elements
A transistor structure comprising:
- a semiconductor material base;
- a semiconductor material mesa upstanding from said base;
- a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
- a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
- first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
- a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
- a plurality of parallel upstanding mesas, wherein each of said upstanding mesas comprises a plurality of first silicide elements spaced along a top mesa surface;
- a plurality of second silicide elements supported on said semiconductor material base and extending along at least a first side of a respective mesa;
- and
- a plurality of first mesa sidewall gate structures respectively provided on a first side of a mesa and comprising a gate insulator material and an overlying gate conductor, each first mesa sidewall gate structure being operative to control current flow between a respective second silicide element and a plurality of spaced first silicide elements associated with a respective mesa.
7 more elements
A transistor structure comprising:
- a semiconductor material base;
- a semiconductor material mesa upstanding from said base;
- a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
- a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
- first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
- a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
- a plurality of mesas comprising a first linearly aligned group of mesas and a second linearly aligned group of mesas, each of said first and second linearly aligned group of mesas comprising at least a first and second mesa within the group;
- a plurality of first silicide elements spaced along a top surface of each mesa, a plurality of second silicide elements supported on said semiconductor material base and extending along at least a first side of said at least first and second mesa of a group;
- and
- a first mesa sidewall gate structure providing on said first side of each said at least first and second mesa of a group and comprising a gate insulator material and an overlying gate conductor, each said first mesa sidewall gate structure being operative to control current flow between a second silicide element common to a group of mesas and a plurality of spaced first silicide elements on the mesas of a group.
7 more elements
A memory structure comprising:
- a plurality of vertical transistors, each transistor comprising:
- a semiconductor material projection extending from a semiconductor material base;
- a plurality of first conductors provided on an upper surface of said projection, the first conductors being formed of silicide;
- a second conductor provided on said base and adjacent to at least a first sidewall of said projection, the second conductor being formed of silicide;
- and
- a first gate structure provided on said first sidewall of said projection for gating current flow between said first and second conductors, at least two of said vertical transistors being provided on each said projection;
- a plurality of memory cells each having a first side connected to a respective first conductor of said at least two vertical transistors;
- and
- a plurality of third conductors respectively connected to a second side of said plurality of memory cells.
6 more elements
An integrated circuit structure comprising:
- a semiconductor substrate containing a plurality of trenches therein defining a plurality of upstanding semiconductor mesas arranged in a pattern of a plurality of linearly extending parallel lines of mesas;
- a plurality of spaced first silicide material areas on an upper surface of each of said mesas;
- a second silicide material on said substrate adjacent to at least a first sidewall of each of said mesas;
- and
- a plurality of gate structures respectively provided at least on said first sidewalls of said mesas arranged in each said line of mesas, such that each of said mesas in a line share a common gate structure at said first sidewall.
2 more elements
Dependencies are inferred from the claim text.