Reduction of edge effects from aspect ratio trapping

A semiconductor structure comprising:

• a crystalline substrate;
• an insulator material defining a plurality of openings to the substrate;
• a plurality of first regions of first crystalline semiconductor material each within a respective one of openings in the insulator, the first crystalline semiconductor material being lattice-mismatched with the crystalline substrate, a majority of defects within the plurality of first regions of first crystalline semiconductor material arising from the lattice mismatch terminating at sidewalls of the openings;
• a plurality of second regions of second crystalline semiconductor material disposed above the first regions;
• a plurality of third regions of third semiconductor material disposed adjacent the plurality of second regions, the third semiconductor material being amorphous;
• and
• wherein top surfaces of the second and third regions define a planar surface.