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US 8,274,068 B2Granted
Semiconductor integrated circuit device and method of fabricating the same
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki Nagashima
Life of this patent
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Abstract
A semiconductor integrated circuit device including: multiple wiring layers stacked on a semiconductor substrate with interlayer insulating films interposed therebetween; wiring hook-up portions extended from the corresponding wirings in the respective wiring layers; and contact conductors so buried in interlayer insulating films as to pass through the hook-up portions for vertically leading wirings of the respective wiring layers, wherein the hook-up portions have different sizes from each other between at least two layers in the wiring layers.
Claims6
A semiconductor integrated circuit device comprising:
- a semiconductor substrate;
- multiple wiring layers stacked on the semiconductor substrate with interlayer insulating films interposed therebetween;
- wiring hook-up portions extended from the corresponding wirings in the respective wiring layers;
- contact conductors so buried in the interlayer insulating films as to pass through the wiring hook-up portions for vertically leading wirings of the respective wiring layers;
- and
- multiple cell array layers;
- wherein
- the wiring hook-up portions have different sizes from each other between at least two layers in the wiring layers;
- word lines and bit lines, which cross each other, are alternately stacked to constitute the multiple wiring layers;
- as the wiring hook-up portions, word line hook-up portions and bit line hook-up portions are disposed in a word line hook-up area and a bit line hook-up area, respectively;
- in the multiple cell array layers, nonvolatile memory cells are arranged at cross-points between the adjacent bit lines and word lines;
- and
- the nonvolatile memory cells are resistance charge type ones, in each of which a variable resistance element and a diode are connected in series.
10 more elements
Dependencies are inferred from the claim text.