# US 8,273,657 B2 · Method for manufacturing a semiconductor apparatus having a through-hole interconnection

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- Number: US 8,273,657 B2
- Document ID: US8273657B2
- Status: Granted
- Kind: B2
- Application number: 13/027,614
- Filed: 2011-02-15
- Published: 2011-06-09
- Granted: 2012-09-25
- Earliest claimed: 2008-01-09
- Assignees: Sony Corporation; Fujikura Ltd.
- Inventors: Yoshimichi Harada; Masami Suzuki; Yoshihiro Nabe; Yuji Takaoka; Tatsuo Suemasu; Hideyuki Wada; Masanobu Saruta
- Web page: https://patentgrep.com/patent/US8273657B2

## CPC

- H10F 39/804: {Containers or encapsulations}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/656: Fan-in layouts
- H10W 72/019: {of bond pads}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. Another insulating layer is formed in the via hole, and a conductive layer of the through-hole interconnection is subsequently formed. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.

## Claims

### Claim 1

A method for manufacturing a semiconductor apparatus having a through-hole interconnection, comprising the steps of:
forming a first insulating layer on a first side of a semiconductor substrate;
forming a first opening for a via hole that extends through the semiconductor substrate to the first insulating layer by etching the semiconductor substrate from a second side thereof, the step of forming the first opening including etching a portion of the semiconductor substrate defining an edge of the first opening at a boundary interface between the semiconductor substrate and the first insulating layer, thereby forming a recessed portion;
forming a second insulating layer on an inside of the first opening so that sidewalls of the first opening and a bottom of the first opening are covered with the second insulating layer, the step of forming the second insulating layer including forming the second insulating layer such that the second insulating layer completely fills the recessed portion in the semiconductor substrate so that an inwardly facing surface of the second insulating layer along an entirety of the sidewall of the first opening is planar;
forming a second opening for the via hole that is in registry with the first opening by etching (i) a portion of the second insulating layer that is formed on the bottom of the first opening and (ii) the first insulating layer formed on the first side of the semiconductor substrate, thereby forming the via hole; and
forming in the via hole a conductive layer for the through-hole connection.

### Claim 2 (depends on 1)

The method of claim 1, further comprising the step of:
forming a third insulating layer inside the via hole prior to the step of forming the conductive layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of forming the conductive layer includes forming the conductive layer on the third insulating layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of forming the conductive layer includes forming the conductive layer on the second insulating layer.