Method to attain low defectivity fully silicided gates

A method of forming a metal oxide semiconductor (MOS) transistor containing a FUSI gate, comprising the steps of:

• forming a protective layer on top surfaces of a polysilicon gate, gate sidewall spacers on lateral surfaces of said gate, and source/drain areas adjacent to said gate sidewall spacers;
• selectively removing said protective layer over said gate whereby said protective layer is not removed from said gate sidewall spacers or said source/drain areas;
• forming a layer of gate metal on a top surface of said gate, in which a composition of said gate metal is selected from the group consisting of nickel and a mixture of nickel and platinum;
• heating said gate metal and said gate so as to form a gate silicide layer in a top region of said gate which is substantially Ni2Si;
• removing said protective layer from said source/drain areas whereby said gate silicide layer in said top region of said gate is not substantially removed;
• forming a layer of source/drain metal on said source/drain areas;
• after heating the gate metal and gate, heating said source/drain metal and said source/drain areas so as to form source/drain silicide layers in top regions of said source/drain areas;
• then, removing unreacted source/drain metal by a process further comprising wet etching, whereby said gate silicide layer in said top region of said gate is not substantially removed;
• and
• after removing the unreacted source/drain metal, annealing said gate and said gate silicide layer in said top region of said gate to form a FUSI gate which is substantially comprised of NiSi.

A method of forming an integrated circuit, comprising the steps of:

• forming a protective layer on top surfaces of a polysilicon n-channel metal oxide semiconductor (NMOS) gate, NMOS gate sidewall spacers on lateral surfaces of said NMOS gate, n-type source/drain (NSD) areas adjacent to said NMOS gate sidewall spacers, polysilicon p-channel metal oxide semiconductor (PMOS) gate, PMOS gate sidewall spacers on lateral surfaces of said PMOS gate, and p-type source/drain (PSD) areas adjacent to said PMOS gate sidewall spacers;
• selectively removing said protective layer over said NMOS gate and said PMOS gate whereby said protective layer is not removed from said NMOS gate sidewall spacers, said NSD areas, said PMOS gate sidewall spacers, or said PSD areas;
• forming a layer of gate metal on top surfaces of said NMOS gate and said PMOS gate;
• heating said gate metal, said NMOS gate and said PMOS gate so as to form:
• an NMOS metal rich silicide layer in a top region of said NMOS gate;
• an intermediate NMOS silicide layer in said NMOS gate below said NMOS metal rich silicide layer;
• an NMOS metal deficient silicide region in said NMOS gate below said intermediate NMOS silicide layer;
• a PMOS metal rich silicide layer in a top region of said PMOS gate;
• an intermediate PMOS silicide layer in said PMOS gate below said PMOS metal rich silicide layer;
• and
• a PMOS metal deficient silicide region in said PMOS gate below said intermediate PMOS silicide layer;
• removing said protective layer from said NSD areas and said PSD areas whereby neither said NMOS metal rich silicide layer in said top region of said NMOS gate or said PMOS metal rich silicide layer in said top region of said PMOS gate are substantially removed;
• forming a layer of source/drain metal on said NSD areas and said PSD areas;
• heating said source/drain metal, said NSD areas and said PSD areas so as to form NSD silicide layers in top regions of said NSD areas and form PSD silicide layers in top regions of said PSD areas, wherein said NSD silicide layers and PSD silicide layer are formed after heating the gate metal;
• removing unreacted source/drain metal by a process further comprising wet etching, whereby neither said NMOS metal rich silicide layer in said top region of said NMOS gate or said PMOS metal rich silicide layer in said top region of said PMOS gate is substantially removed;
• and
• after removing unreacted source/drain metal, annealing said NMOS gate and said PMOS gate and to form an NMOS FUSI gate which has said desired FUSI stoichiometry and form a PMOS FUSI gate which has said desired FUSI stoichiometry.