Method of fabricating an NMOS transistor
AssigneeUnited Microelectronics Corp.
InventorsChen-Hua Tsai, Po-Jui Liao, Tzu-Feng Kuo, Ching-I Li, Cheng-Tzung Tsai
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Abstract
A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.
Claims18
A method for fabricating an NMOS transistor, comprising:
- providing a silicon substrate having a gate structure thereon;
- forming a first spacer on a sidewall of the gate structure;
- forming a lightly doped drain (LDD) region in the silicon substrate at each of two sides of the gate structure;
- forming a second spacer on the first spacer;
- and
- after forming the second spacer, forming a silicon carbide region and a source/drain region in the silicon substrate at each of two sides of gate structure, wherein the silicon carbide region comprises a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region, and a second concentration of crystalline silicon carbide in the second portion is higher than a first concentration of crystalline silicon carbide in the first portion.
A method for fabricating an NMOS transistor, comprising:
- providing a silicon substrate having a gate structure thereon;
- forming a first spacer on a sidewall of the gate structure;
- implanting carbon atoms at a normal angle into the silicon substrate for pre-amorphorizing the silicon of the silicon substrate in a predetermined source/drain region and beneath a predetermined lightly doped drain (LDD) region at each of the two sides of the gate structure;
- after implanting the carbon atoms, implanting an n type dopant into the silicon substrate in the predetermined LDD regions;
- performing a rapid thermal process for forming the crystalline silicon carbide and simultaneously forming the LDD regions;
- forming a second spacer on the first spacer;
- and
- forming a source/drain region in the silicon substrate at each of the two sides of gate structure, wherein the silicon carbide region comprises a first portion overlapping the source/drain region and a second portion underneath the LDD region, and a second concentration of crystalline silicon carbide in the second portion is higher than a first concentration of crystalline silicon carbide in the first portion.
Dependencies are inferred from the claim text.