# US 8,273,632 B2 · Patterning methodology for uniformity control

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- Number: US 8,273,632 B2
- Document ID: US8273632B2
- Status: Granted
- Kind: B2
- Application number: 13/281,862
- Filed: 2011-10-26
- Published: 2012-05-03
- Granted: 2012-09-25
- Earliest claimed: 2010-11-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu Chao Lin; Ming-Ching Chang; Yih-Ann Lin; Ryan Chia-Jen Chen; Chao-Cheng Chen
- Web page: https://patentgrep.com/patent/US8273632B2

## CPC

- H10P 50/71: {using masks for conductive or resistive materials}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 50/287: {by chemical means}
- H10P 76/2043: {using an anti-reflective coating}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
forming a polysilicon layer over a substrate, the substrate having a topography variation;
forming a first layer over the polysilicon layer, the first layer having a thickness that substantially exceeds the topography variation of the substrate;
forming a second layer over the first layer;
patterning the second layer to form a patterned second layer that has a plurality of components separated by a plurality of openings;
patterning the first layer with the patterned second layer to form a patterned first layer; and
patterning the polysilicon layer with the patterned first layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the patterning the second layer is carried out in a manner such that at least one of the components of the second layer is correlated to a critical dimension of the semiconductor device.

### Claim 3 (depends on 2)

The method of claim 2, wherein the at least one of the components of the second layer has a width that is approximately equal to the critical dimension of the semiconductor device.

### Claim 4 (depends on 1)

The method of claim 1, wherein the patterning the first layer includes performing an etching process in which the first layer and the second layer have substantially different etching rates.

### Claim 5 (depends on 1)

The method of claim 1, wherein the thickness of the first layer exceeds the topography variation of the substrate by a factor greater than or equal to about ten.

### Claim 6 (depends on 1)

The method of claim 1, further including: after the forming the polysilicon layer and before the forming the first layer, forming a hard mask layer over the polysilicon layer, wherein the hard mask layer is formed between the polysilicon layer and the first layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the patterning the polysilicon layer forms a plurality of polysilicon gates; and further including: after the patterning the polysilicon layer, replacing the polysilicon gates with a plurality of metal gates.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
the first layer contains an anti-reflective material; and
the second layer contains a dielectric material or an organic material.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
the first layer contains carbon and hydrogen; and
the second layer contains nitrogen.

### Claim 10

A method of fabricating a semiconductor device, comprising:
forming a patternable layer over a substrate;
forming a first layer over the patternable layer;
forming a second layer over the first layer, the first and second layers having different material compositions and substantially different thicknesses;
performing a first etching process to the second layer to form a plurality of second layer components, wherein at least a subset of the second layer components each define a critical dimension of the semiconductor device;
performing a second etching process to the first layer to form a plurality of first layer components, wherein the second etching process is performed using the second layer components as etching masks; and
performing a third etching process to the patternable layer, wherein the third etching process is performed using the first layer components as etching masks.

### Claim 11 (depends on 10)

The method of claim 10, wherein the substrate has a topography variation that is a fraction of the thickness of the first layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the second etching process is tuned to have an etching selectivity greater than ten between the first layer and the second layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein the patternable layer includes a polysilicon material.

### Claim 14 (depends on 10)

The method of claim 10, wherein the patternable layer includes a dielectric material.

### Claim 15 (depends on 10)

The method of claim 10, wherein:
the first layer is an anti-reflective layer that contains carbon and hydrogen; and
the second layer is a dielectric layer or an organic layer.

### Claim 16

A method of fabricating a semiconductor device, comprising:
forming a polysilicon layer over a substrate, the substrate having an amount of variation in topography;
forming an anti-reflective layer over the polysilicon layer, the anti-reflective layer being multiple times thicker than the amount of variation in the topography of the substrate;
forming a sacrificial layer over the anti-reflective layer, the sacrificial layer being substantially thinner than the anti-reflective layer;
patterning the sacrificial layer to form a plurality of sacrificial features, wherein at least one of the sacrificial features has a width that is a function of a critical dimension of the semiconductor device;
patterning the anti-reflective layer using the sacrificial features as masks; and
thereafter patterning the polysilicon layer using the patterned anti-reflective layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the anti-reflective layer is at least ten times thicker than the amount of variation in the topography of the substrate; and
the width of the at least one of the sacrificial features and the critical dimension have a ratio that approaches 1:1.

### Claim 18 (depends on 16)

The method of claim 16, wherein the patterning the polysilicon layer forms a plurality of polysilicon gate components; and further including: replacing the polysilicon gate components with a plurality of metal gate components, respectively.

### Claim 19 (depends on 16)

The method of claim 16, wherein the patterning the anti-reflective layer is carried out using a dry etching process in which the sacrificial layer and the anti-reflective layer have substantially different etching rates.

### Claim 20 (depends on 16)

The method of claim 16, wherein:
the anti-reflective layer contains carbon and hydrogen; and
the sacrificial layer contains a dielectric material or an organic material.