# US 8,273,622 B2 · Semiconductor with a dynamic gate-drain capacitance

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- Number: US 8,273,622 B2
- Document ID: US8273622B2
- Status: Granted
- Kind: B2
- Application number: 13/161,050
- Filed: 2011-06-15
- Published: 2011-10-06
- Granted: 2012-09-25
- Earliest claimed: 2008-08-01
- Assignees: Infineon Technologies Austria AG
- Inventors: Anton Mauder; Hans-Joachim Schulze; Carolin Tolksdorf; Winfried Kaindl; Armin Willmeroth
- Web page: https://patentgrep.com/patent/US8273622B2

## CPC

- H10P 30/21: {of electrically active species}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 84/215: {of only varactors}
- H10D 84/217: {of only conductor-insulator-semiconductor capacitors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/839: {comprising VDMOS}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate comprising a drift region of a first conductivity type;
forming at least a first body region of a second conductivity type in the semiconductor substrate;
forming at least a depletable region of the second conductivity type adjoining the first body region in the semiconductor substrate;
forming at least a source region of the first conductivity type in the semiconductor substrate such that the first body region is arranged between the drift region and the source region;
forming an insulation structure on the semiconductor substrate; and
forming at least an electrode structure on the insulation structure such that the electrode structure being arranged at least in portions next to the first body region and at least in portions next to the depletable region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a second body region of the second conductivity adjacent to the first body region, wherein the first and second body regions are formed by implanting a dopant of the second conductivity type.

### Claim 3 (depends on 2)

The method of claim 2, comprising:
forming the electrode structure before forming the first and second body regions; and
using the electrode structure as implantation mask for implanting the dopant of the second conductivity type to form the first and second body regions in a self-aligned manner with respect to the electrode structure.

### Claim 4 (depends on 2)

The method of claim 2, further comprising providing a further mask and implanting separately a dopant of the second conductivity type using the further mask as implantation mask to form the depletable region connecting the first and second doping regions.

### Claim 5 (depends on 3)

The method of claim 3, further comprising performing at least one thermal annealing step after implanting the dopant of the second conductivity type, wherein the annealing step is performed such that the implanted dopant of the second conductivity is diffused so that the depletable region connecting first and second doping regions is formed.

### Claim 6 (depends on 5)

The method of claim 5, wherein the electrode structure is formed to comprise at least a first electrode portion comprising a lateral width d1 and a second electrode portion comprising a lateral width d2, wherein the first and second electrode portions are electrically connected with each other, and wherein d1 is larger than d2.

### Claim 7 (depends on 5)

The method of claim 5, comprising performing the process of forming the source region after the thermal annealing process and comprises implanting a dopant of the first conductivity type while using the electrode structure as implantation mask.

### Claim 8

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate comprising a drift region of a first conductivity type;
forming an insulation structure on the semiconductor substrate;
forming at least an electrode structure arranged on the insulation structure such that the electrode structure comprises at least an electrode portion comprising a lateral width d2;
implanting a dopant of a second conductivity type into the drift region using the electrode portion as implantation mask such that a first doping region and a second doping region of the second conductivity type are formed, wherein the first and second doping regions are laterally spaced from each other;
performing at least one thermal anneal for diffusing the implanted dopant to form a first and second body region; and
wherein the lateral width d2 and the thermal anneal are selected such that the doping regions diffuses together and form a depletable region of the second conductivity type which connects the first and second body regions.

### Claim 9 (depends on 8)

The method of claim 8, further comprising implanting a dopant of the first conductivity type after performing the thermal annealing process with the electrode structure being used as implantation mask to form a source region.