US 8,271,700 B1 · Logical address direct memory access with multiple concurrent physical ports and internal switching

Abstract

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Claims19

Dependent claims

A method for operating a direct memory access (DMA) engine for data transfer operations, comprising:

concurrently fetching at least two DMA descriptors, each of the at least two DMA descriptors corresponding to respective data transfer operations between devices;
processing each of the at least two DMA descriptors for
determining a source device and a destination device, read address information of data to be read from the source device and write address information of the destination device where the data is to be written, and
executing logical to physical address translation of at least one of the read address information and the write address information;
generating multiple read and write commands corresponding to each of the at least two DMA descriptors;
executing concurrent data transfer of data between source ports and destination ports of the DMA engine in response to the read and write commands;
and,
reporting in order DMA completion status for each of the at least two DMA descriptors.

5 more elements

Dependencies are inferred from the claim text.

Logical address direct memory access with multiple concurrent physical ports and internal switching

Life of this patent

Logical address direct memory access with multiple concurrent physical ports and internal switching

Life of this patent

Abstract

Claims19