US 8,266,620 B2 · Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Abstract

A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.

Claims12

Dependent claims

A multiprocessing system, comprising:

a multithreading microprocessor, comprising:
a plurality of thread contexts (TCs);
and
a virtual processing element (VPE), configured to receive a plurality of interrupt requests, wherein said interrupt requests are non-specific to said plurality of TCs, wherein said VPE is configured to select one of said plurality of TCs to execute a thread to service an active one of said interrupt requests and to set a control bit to disable said VPE from servicing any of said interrupt requests,
said VPE comprising a first register for globally masking individual ones of said interrupt requests and their sources that are active from being serviced by any of said plurality of TCs of said VPE and wherein each of said plurality of TCs comprise a second register;
and
a multiprocessor operating system (OS), comprising said interrupt service thread, for execution on said selected TC, configured to save information indicating which ones of said plurality of interrupt requests is active in said second register of said TC selected by said VPE to execute said interrupt service thread and to write to said first register to globally mask said active one of said interrupt requests, prior to clearing said control bit, in order to prevent said VPE from selecting a different one of said plurality of TCs to redundantly service said active interrupt request between clearing said control bit and clearing the sources of said active interrupt requests.

4 more elements

A method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs) and a virtual processing element (VPE), configured to receive a plurality of interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select one of the plurality of TCs to execute a thread to service an active one of the interrupt requests and to set a control bit to disable the VPE from servicing any of the interrupt requests, the VPE comprising a first register for globally masking individual ones of the interrupt requests and their sources that are active from being serviced by any of the plurality of TCs of the VPE and wherein each of the plurality of TCs comprise a second register, the method comprising:

the interrupt service thread executing on the selected TC:
saving information indicating which ones of the plurality of interrupt requests is active in the second register of said TC selected by the VPE to execute the interrupt service thread;
and
writing to the first register to globally mask the active one of the interrupt requests, prior to clearing the control bit, in order to prevent the VPE from selecting a different one of the plurality of TCs to redundantly service the active interrupt request between clearing the control bit and clearing the sources of the active interrupt requests.

1 more element

Dependencies are inferred from the claim text.

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Life of this patent

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Life of this patent

Abstract

Claims12