Verification apparatus, verification method, and computer-readable recording medium for supporting engineering change order

A verification method for verifying a circuit to be verified in a case where a logic change has been made to a reference circuit and the circuit to be verified that has been created from the reference circuit in a semiconductor design step, comprising the steps of:

• (a) extracting, by a computer, from the reference circuit in a state before the logic change and in a state after the logic change, a point where an input value of a signal changes due to the logic change, based on information regarding a signal that has changed due to the logic change in the reference circuit;
• (b) extracting, by the computer, from the circuit to be verified in a state before the logic change and in a state after the logic change, a point where an input value of a signal changes due to the logic change, based on information regarding a signal that has changed due to the logic change in the circuit to be verified;
• and
• (c) generating, by the computer a verification script for verifying the circuit to be verified, with use of the point extracted in the step (a) and the point extracted in the step (b), wherein in the step (a), information that specifies a signal that has changed due to the logic change in the reference circuit, a signal included in an instance that has been deleted from the reference circuit due to the logic change, and a signal included in an instance that has been added to the reference circuit due to the logic change, is acquired as the information regarding the signal that has changed due to the logic change in the reference circuit, and
• in the step (b) information that specifies a signal that has changed due to the logic change in the circuit to be verified, a signal included in an instance that has been deleted from the circuit to be verified due to the logic change, and a signal included in an instance that has been added to the circuit to be verified due to the logic change, is acquired as the information regarding the signal that has changed due to the logic change in the circuit to be verified,
• wherein in the step (a), a register or an external output terminal that exists on a route for each signal specified by the information acquired in the step (a) is specified, and the specified register or the specified external output terminal is extracted as the point in the reference circuit if the specified register or the specified external output terminal exists in the reference circuit in both the state before the logic change and the state after the logic change, and
• in the step (b), a register or an external output terminal that exists on a route for each signal specified by the information acquired in the step (b) is specified, and the specified register or the specified external output terminal is extracted as the point in the circuit to be verified if the specified register or the specified external output terminal exists in the circuit to be verified in both the state before the logic change and the state after the logic change.

A computer-readable recording medium having recorded thereon a program for, with use of a computer, verifying a circuit to be verified in a case where a logic change has been made to a reference circuit and the circuit to be verified that has been created from the reference circuit in a semiconductor design step, the program including instructions for causing the computer to execute the steps of:

• (a) extracting, from the reference circuit in a state before the logic change and in a state after the logic change, a point where an input value of a signal changes due to the logic change, based on information regarding a signal that has changed due to the logic change in the reference circuit;
• (b) extracting, from the circuit to be verified in a state before the logic change and in a state after the logic change, a point where an input value of a signal changes due to the logic change, based on information regarding a signal that has changed due to the logic change in the circuit to be verified;
• and
• (c) generating a verification script for verifying the circuit to be verified, with use of the point extracted in the step (a) and the point extracted in the step (b),
• wherein in the step (a), information that specifies a signal that has changed due to the logic change in the reference circuit, a signal included in an instance that has been deleted from the reference circuit due to the logic change, and a signal included in an instance that has been added to the reference circuit due to the logic change, is acquired as the information regarding the signal that has changed due to the logic change in the reference circuit, and
• in the step b information that specifies a signal that has changed due to the logic change in the circuit to be verified, a signal included in an instance that has been deleted from the circuit to be verified due to the logic change, and a signal included in an instance that has been added to the circuit to be verified due to the logic change, is acquired as the information regarding the signal that has changed due to the logic change in the circuit to be verified,
• wherein in the step (a), a register or an external output terminal that exists on a route for each signal specified by the information acquired in the step (a) is specified, and the specified register or the specified external output terminal is extracted as the point in the reference circuit if the specified register or the specified external output terminal exists in the reference circuit in both the state before the logic change and the state after the logic change, and
• in the step (b), a register or an external output terminal that exists on a route for each signal specified by the information acquired in the step (b) is specified, and the specified register or the specified external output terminal is extracted as the point in the circuit to be verified if the specified register or the specified external output terminal exists in the circuit to be verified in both the state before the logic change and the state after the logic change.