Multi-mode redundancy removal
AssigneeSynopsys, Inc.
InventorsStephen M. Plaza, Prashant Saxena, Pei-Hsin Ho, Thomas R. Shiple
Life of this patent
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Abstract
A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.
Claims39
A method of providing redundancy removal in a design for an integrated circuit, the method comprising:
- accessing the design;
- starting to perform a full-scale redundancy removal;
- determining whether a predetermined period for performing the full-scale redundancy removal has reached a first cut-off;
- using a computer, when the first cut-off has been reached, then determining a location for temporary outputs of the design, creating the temporary outputs, and performing a localized redundancy removal up to the temporary outputs;
- and
- outputting an optimized design based on the full-scale redundancy removal up to the first cut-off and the localized redundancy removal.
A computer-readable medium storing instructions for providing redundancy removal in a design for an integrated circuit, the instructions, when executed by a processor, performing steps comprising:
- accessing the design;
- starting to perform a full-scale redundancy removal on the design;
- determining whether a predetermined period for performing the full-scale redundancy removal has reached a first cut-off;
- when the first cut-off has been reached, then determining a location for temporary outputs of the design, creating the temporary outputs, and performing a localized redundancy removal up to the temporary outputs;
- and
- outputting an optimized design based on the full-scale redundancy removal up to the first cut-off and the localized redundancy removal.
A synthesis and design for test system including a processor configured with processor-executable instructions for providing redundancy removal in a design for an integrated circuit, the processor-executable instructions performing steps comprising:
- accessing the design;
- starting to perform a full-scale redundancy removal on the design;
- determining whether a predetermined period for performing the full-scale redundancy removal has reached a first cut-off;
- using the processor, when the first cut-off has been reached, then determining a location for temporary outputs of the design, creating the temporary outputs, and performing a localized redundancy removal up to the temporary outputs;
- and
- outputting an optimized design based on the full-scale redundancy removal up to the first cut-off and the localized redundancy removal.
Dependencies are inferred from the claim text.