Back to results
US 8,266,562 B2Granted
Method and system for configurable contacts for implementing different bias designs of an integrated circuit device
OwnerRobert Paul Masleid, Steven T. Stoiberinventors
Life of this patent
Estimating the term…
Abstract
In a computer implemented synthesis system, a fabrication method for an integrated circuit device. The method includes receiving a circuit netlist representing a first form of an integrated circuit design to be realized in physical form. A plurality of contacts of the netlist are accessed. The plurality of contacts are configured to implement a second form of the integrated circuit design.
Claims20
A method comprising:
- using a computer to generate a circuit layout including a circuit element;
- if a state of the circuit element in the circuit layout is a first state, allowing the circuit element in a mask generation process for fabrication of the circuit layout;
- and
- if the state is a second state, omitting the circuit element from the mask generation process for fabrication of the circuit layout.
1 more element
A method comprising:
- using a computer to generate a circuit layout including a first version of a circuit element and a second version of the circuit element;
- if a state of the first version of the circuit element is a first state, allowing the first version of the circuit element and the second version of the circuit element in a mask generation process for fabrication of the circuit layout;
- and
- if the state of the first version is a second state, omitting the first version of the circuit element from the mask generation process for fabrication of the circuit layout and allowing the second version of the circuit element in the mask generation process for fabrication of the circuit layout.
1 more element
A computer-readable storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:
- instructions to allow a circuit element of a circuit layout in a mask generation process for fabrication of the circuit layout if a state of the circuit element is a first state;
- and
- instructions to omit the circuit element from the mask generation process for fabrication of the circuit layout if the state is a second state.
Dependencies are inferred from the claim text.