Methods for forming arrays of small, closely spaced features
AssigneeMicron Technology, Inc.
InventorDavid H. Wells
Life of this patent
Estimating the term…
Abstract
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.
Claims7
An array of features for computer memory fabrication, comprising:
- a middle tier comprising a grid with crossing grid lines extending on a same level, holes between the grid lines, and grid line intersections where the grid lines cross, the grid lines having sidewalls;
- a lower tier comprising a surface upon which the grid is positioned, the holes extending to the lower tier;
- and
- a higher tier comprising pillars positioned on the grid at the grid line intersections, the pillars having sidewalls and substantially localized at the grid line intersections.
Dependencies are inferred from the claim text.