Stripe based memory operation

A method for stripe-based memory operation, comprising:

• writing original data in a first stripe across a storage volume of a plurality of memory devices;
• updating at least a fragment of the written original data, wherein updating includes writing updated data in a second stripe without reading or copying the written original data;
• and
• wherein the method includes writing unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe.

A method for stripe-based memory operation, comprising:

• writing data in a stripe across a storage volume of a plurality of memory devices;
• detecting an error associated with a portion of the stripe;
• effectively removing the portion of the stripe from the stripe in response to detecting the error;
• and
• operating the stripe without the removed portion.

Memory system control circuitry, comprising:

• non-volatile memory control circuitry configured to:
• write original data associated with a plurality of addresses in a first stripe across a plurality of channels;
• write updated data associated with at least one of the plurality of addresses in a second stripe across the plurality of channels without reading or copying the original data in the first stripe;
• and
• write unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe.

Memory system control circuitry, comprising:

• non-volatile memory control circuitry configured to:
• write received data in a stripe across a plurality of channels;
• and
• detect an error associated with a portion of the stripe;
• and
• memory management circuitry configured to effectively remove the portion of the stripe from the stripe in response to the non-volatile memory control circuitry detecting the error;
• wherein the non-volatile memory control circuitry is further configured to operate the stripe without the removed portion of the stripe.

A memory system, comprising:

• control circuitry;
• and
• a plurality of solid state memory devices, wherein:
• each of the plurality of solid state memory devices is coupled to the control circuitry by a respective one of a plurality of channels;
• and
• the plurality of solid state memory devices provide a storage volume for the memory system;
• wherein the control circuitry is configured to:
• write data in a stripe across the storage volume of the plurality of solid state memory devices across the plurality of channels;
• read data from a portion of the stripe across one of the plurality of channels;
• and
• reclaim portions of the storage volume on a stripe-basis in response to one or more of the group including:
• all portions of the particular stripe having an invalid indication in the block table;
• and
• a garbage collection threshold amount of portions of the particular stripe having an invalid indication in the block table, wherein the threshold amount of portions is greater than one and less than all portions.

A method for stripe-based memory operation, comprising:

• writing original data in a first stripe across a storage volume of a plurality of memory devices;
• updating at least a fragment of the written original data, wherein updating includes writing updated data in a second stripe without reading or copying the written original data;
• calculating respective first level error correction data based on each fragment of the original data;
• calculating second level error correction data based on the original data;
• wherein writing the original data includes writing the original data and the first level error correction data in a first subset of the plurality of memory devices, and writing the second level error correction data in a second subset of the plurality of memory devices;
• detecting an error in a fragment of original data in the first stripe, wherein the error is uncorrectable with the first level error correction data;
• and
• correcting the error, wherein correcting the error includes:
• creating replacement data for the fragment of original data based on at least a remainder of the original data and the second level error correction data in the first stripe;
• and
• writing the replacement data in a third stripe without writing the remainder of the original data in the third stripe.

A memory system, comprising:

• control circuitry;
• a volatile memory coupled to the control circuitry and storing a block table;
• a plurality of solid state memory devices, wherein:
• each of the plurality of solid state memory devices is coupled to the control circuitry by a respective one of a plurality of channels;
• the plurality of solid state memory devices provide a storage volume for the memory system;
• and
• a copy of the block table is stored in at least one of the plurality of solid state memory devices;
• wherein the control circuitry is configured to:
• write data in a stripe across the storage volume of the plurality of solid state memory devices across the plurality of channels;
• read data from a portion of the stripe across one of the plurality of channels;
• reclaim portions of the storage volume on a stripe-basis;
• maintain a block table with information regarding validity of portions of the stripe;
• indicate that a portion of the stripe is invalid in the block table in response to updated data corresponding to the portion of the stripe being written to another stripe;
• and
• operate the stripe without the invalid portion.