Systems and methods for performing concatenated error correction
AssigneeMarvell World Trade Ltd.
InventorsXueshi Yang, Zining Wu, Seo-How Low
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Abstract
A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
Claims11
An apparatus for encoding data, the apparatus comprising:
- an outer encoder configured to generate a code word corresponding to received input data;
- a de-multiplexer configured to divide the code word into sub-sectors of data, wherein the sub-sectors of data are divided based upon memory capacities of memory cells into which the received input data is to be written;
- a parity circuit configured to
- divide the sub-sectors of data into groups of logical cells of data, wherein each group of logical cells of data includes a first logical cell, and
- compute parities of the groups of logical cells of data;
- and
- an inner encoder configured to
- generate error correction bits for at least some of the first logical cells based on parities of the groups of logical cells of data, and
- insert the error correction bits into at least some of the first logical cells to create encoded data.
A method for encoding data by using an encoder, the method comprising:
- generating a code word corresponding to received input data;
- based upon memory capacities of memory cells into which the received input data is to be written, dividing the code word into sub-sectors of data;
- dividing the sub-sectors of data into logical cells of data, wherein each group of logical cells includes a first logical cell;
- computing parities of the groups of logical cells of data;
- based on parities of the groups of logical cells of data, generating an error correction bit for at least some of the first logical cells;
- and
- inserting the error correction bit into the at least some of the first logical cells.
Dependencies are inferred from the claim text.