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US 8,266,494 B2Granted
Bus with error correction circuitry
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsRichard Ferrant, Cédric Maufront
Life of this patent
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Abstract
A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
Claims10
A circuit comprising:
- a first data bus comprising a plurality of first logic blocks coupled in series, each logic block comprising at least one first buffer for buffering at least one data bit transmitted via said data bus and at least some of said first logic blocks further comprising circuitry coupled in parallel with said at least one first buffer and arranged to determine a first bit of error correction code associated with said at least one data bit;
- and
- a second data bus coupled to said first data bus and comprising a plurality of second logic blocks coupled in series, each second logic block comprising at least one second buffer for buffering at least one data bit transmitted via said second data bus and at least some of said second logic blocks further comprising circuitry coupled in parallel with said at least one second buffer arranged to determine a second bit of error correction code and to compare said first and second bits of error correction code.
A method of transmitting data via a data bus comprising:
- in a first data bus:
- buffering at least one bit of said data using at least one first buffer of a first logic block;
- and
- in parallel with the buffering of said at least one bit of said data by said at least one first buffer, determining by said first logic block at least one bit of error correction code associated with said at least one bit of said data;
- and
- in a second data bus coupled to said first data bus:
- buffering said at least one bit of said data using at least one second buffer of a second logic block;
- and
- in parallel with the buffering of said at least one bit of said data by said at least one second buffer, determining, by said second logic block, a second bit of error correction code and comparing said first and second bits of error correction code.
6 more elements
Dependencies are inferred from the claim text.