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US 8,266,493 B1Granted
Low-density parity check decoding using combined check node and variable node
AssigneeL-3 Communications Corporation
InventorsAyyoob Abbaszadeh, Ryan Hinton
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Abstract
A technique for decoding low-density parity check codes includes performing a combined check node and variable node calculation. Decoding is initialized using channel likelihood values estimated from a received physical signal. The decoding iteratively updates the variable nodes. Performing a combined check node and variable node calculation can enable reduced memory usage and faster convergence for the decoder.
Claims18
A decoder for a quasi-cyclical low-density parity check code, comprising:
- a plurality of node processors each configured to perform a combined check node and variable node calculation on a variable node likelihood value at an input of the node processor using a check to variable node message to produce an updated variable node likelihood value at an output of the node processor
- a plurality of variable node memories providing storage for a plurality of variable node likelihood values, wherein the plurality of variable node memories comprise shift registers, each of the shift registers having a fixed time delay and connecting an output of one of the node processors to an input of one of the node processors;
- and
- a plurality of message memories coupled to the node processors, each message memory being associated with one of the node processors and having storage for a plurality of the check to variable node messages.
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A method of decoding a quasi-cyclical low-density parity check code, the method comprising:
- obtaining initial variable node likelihood values for symbols in a received signal;
- performing, in a plurality of node processors with check to variable node messages stored in a plurality of message memories, combined check node and variable node calculations on the variable node likelihood values at inputs of the node processors to update the variable node likelihood values;
- providing the updated variable node likelihood values from outputs of the node processors through fixed time delay paths to inputs of at least some of the node processors, wherein each of the fixed time delay paths comprises a shift register connecting an output of one of the node processors to an input of one of the node processes;
- and
- repeating the performing and the providing until a predefined exit criterion is reached.
2 more elements
Dependencies are inferred from the claim text.